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ics for communications pci interface for telephony/data applications pita psb 4600 version 1.2 preliminary data sheet 12.98 ds 1
psb 4600 revision history: current version: 12.98 previous version: page (in previous version) page (in current version) subjects (major changes since last revision) all all new release in information mapping ? for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide: see our webpage at http://www.siemens.de/semiconductor/address/address.htm. edition 12.98 published by siemens ag, hl sp, balanstra?e 73, 81541 mnchen ? siemens ag 1998. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? , digitape ? are trademarks of siemens ag.
psb 4600 semiconductor group 3 preliminary data sheet 12.98 organization of this data sheet this preliminary data sheet is divided into 13 chapters: ? chapter 1, features describes the compliants, interfaces and the compatibilities of the pita. ? chapter 2, applications realized with the pita describes the applications realized with the pita. ? chapter 3, construction of the pita shows a block diagram and describes the interfaces and their functions. ? chapter 4, communication with the pita describes the different controllers, registers and the power management of the pita. ? chapter 5, communication with external components gives a general description of the interfaces and modes of the pita. ? chapter 6, configuration of the pita describes the pinstrapping and pins used for pinstrapping during system reset. ? chapter 7, pinning describes the pins, types of pins and the characteristics of the interfaces. ? chapter 8, package outlines describes the package outlines. ? chapter 9, precaution s describes electrical maximum ratings and electrical characteristics. ? chapter 10, configuration space register of the pita contains maps and descriptions of the pci configuration space registers of the pita. ? chapter 11, internal register of the pita contains maps and descriptions of the internal registers of the pita. ? chapter 12, abbreviations describes abbreviations occuring in this data sheet. ? chapter 13, index
psb 4600 semiconductor group 4 preliminary data sheet 12.98 important notes about this data sheet ________________________________________ whats new? the organization of the structure follows the guidelines of information mapping ? . ________________________________________ what is information mapping ? ? this is a research based method for the Canalysis Cstructure C presentation of user-orientated manuals. ________________________________________ major changes instead of the used chapters with mono causal descriptions you now get C all information C for a scope C under the corresponding heading. ________________________________________ the intention this data sheet is intended to be C easily surveyed C increasingly readable C customized applicable C practice-orientated C offering the quickest possible way to the required information. ________________________________________
psb 4600 semiconductor group 5 preliminary data sheet 12.98 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 applications realized with the pita . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 construction of the pita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 4 communication with the pita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 information about the pci configuration space . . . . . . . . . . . . . . . . . . 4-3 4.1.2 access to the pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.1.3 base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.1.4 other registers of the pci configuration space . . . . . . . . . . . . . . . . . 4-11 4.2 pci master target controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.1 supported pci commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.2.2 transaction type single data read . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.2.3 transaction type single data write . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 4.2.4 transaction type burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 4.2.5 transaction type burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4.2.6 transaction type fast back to back . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4.3 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24 4.3.1 information about the power management states . . . . . . . . . . . . . . . 4-25 4.3.2 configuration space registers of the power management . . . . . . . . . 4-28 4.4 interrupt control register - retry counter . . . . . . . . . . . . . . . . . . . . . . . . 4-35 5 communication with external components . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 serial dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.1.2 iom-2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.1.3 iom-2 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.1.4 iom-2 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.1.5 iom-2 modes - supplementary description . . . . . . . . . . . . . . . . . . . . . 5-24 5.1.6 single modem mode v2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.1.7 single modem mode alis v3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.1.8 dual modem/modem+voice mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 5.1.9 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45 5.2 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-47 5.2.1 ale after system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-50 5.2.2 ale after internal software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-51 5.2.3 ale after setting the parallel interface mode bit . . . . . . . . . . . . . . . . . 5-52 5.2.4 non multiplexed mode (write transaction) . . . . . . . . . . . . . . . . . . . . . 5-53 5.2.5 non multiplexed mode (read transaction) . . . . . . . . . . . . . . . . . . . . . 5-54 5.2.6 multiplexed mode (write transaction) . . . . . . . . . . . . . . . . . . . . . . . . . 5-55 5.2.7 multiplexed mode (read transaction) . . . . . . . . . . . . . . . . . . . . . . . . . 5-56 5.2.8 transaction disconnect with target abort . . . . . . . . . . . . . . . . . . . . . . 5-57 5.2.9 transaction termination with retry . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-60
psb 4600 semiconductor group 6 preliminary data sheet 12.98 5.2.10 timing of the parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-62 5.3 general purpose i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-65 5.3.1 information about the gp i/o interface . . . . . . . . . . . . . . . . . . . . . . . . 5-66 5.3.2 timing of the gp i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-68 5.3.3 internal registers of the gp i/o interface . . . . . . . . . . . . . . . . . . . . . . 5-69 5.3.4 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-76 5.3.5 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-78 5.3.6 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-80 5.3.7 usage of the gp i/o interface as alis v2.1 control interface . . . . . . 5-82 5.4 spi eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-84 5.4.1 information about the spi eeprom interface . . . . . . . . . . . . . . . . . . 5-85 5.4.2 timing of the spi eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . 5-88 5.4.3 internal registers for the spi eeprom interface . . . . . . . . . . . . . . . . 5-90 6 configuration of the pita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 7 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 9 precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.4 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 10 configuration space register of the pita . . . . . . . . . . . . . . . . . . . . . 10-1 10.1 description of the register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.2 configuration space register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.3 registers which do not occur elsewhere in the data sheet . . . . . . . . . 10-13 11 internal register of the pita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1 description of the register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.2 internal register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.3 registers which do not occur elsewhere in the data sheet . . . . . . . . . 11-10 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 13 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
psb 4600 semiconductor group 0-1 preliminary data sheet 12.98 introduction ________________________________________ what is the pita? the pita is a cost-effective pci bridge for industrial and communication applications. ________________________________________ the pita can be used in ? pci isdn cards. ? pci hardware modems. ? pci software modems. ? industrial pci bridge applications. ________________________________________ interfaces of the pita the pita offers the following interfaces: interfaces to find in pci master target controller see chapter 4.2 on page 4-13 serial dma interface see chapter 5.1 on page 5-2 parallel interface see chapter 5.2 on page 5-47
psb 4600 semiconductor group 0-2 preliminary data sheet 12.98 general purpose i/o interface see chapter 5.3 on page 5-65 spi eeprom interface see chapter 5.4 on page 5-84 the pita offers the following interfaces: interfaces to find in
psb 4600 features semiconductor group 1-1 preliminary data sheet 12.98 1 features ________________________________________ compliant with ?pc98 ? pci bus specification version 2.2 ? pci power management specification version 1.0 ________________________________________ interfaces ? pci master target interface C pci 2.2 compliant C32 bit C33 mhz ? serial interface C supports iom-2 modes C supports serial interface to the alis chip-set family C dma controller for serial communication C 16 word fifos for each direction ? parallel interface with chip select logic supporting up to three external components ? general purpose i/o interface with interrupt capability ? spi tm interface for optional eeprom ________________________________________
psb 4600 features semiconductor group 1-2 preliminary data sheet 12.98 ________________________________________ compatibility ? alis v2.1 psb 4596 ? alis v3.x psb 4596 ? isdn iom-2 components, e.g.: C iec-q family C sbcx ? components consisting of a parallel multiplexed or non multiplexed intel interface, e.g: C ipac C isac C isar ________________________________________
psb 4600 applications realized with the pita semiconductor group 2-1 preliminary data sheet 12.98 2 applications realized with the pita ________________________________________ overview the pita provides a pci interface supporting a serial and parallel interface, including communication applications such as analog software modems and hardware isdn modems. ________________________________________ note the name alis referes to the alis chip-set (analog line interface solution), consting of alis-a (psb4595) and alis-d (psb4596). ________________________________________ isdn-s interface application with the ipac ________________________________________ psb 4600 pita eeprom spi pci bus psb 2115 ipac microcontroller interface s-interface
psb 4600 applications realized with the pita semiconductor group 2-2 preliminary data sheet 12.98 ________________________________________ isdn-u interface application with the 3pac and iec-q te ________________________________________ software modem using the alis-a and alis-d with pci interface ________________________________________ psb 4600 pita eeprom spi pci bus psb 2113 3pac microcontroller interface psb 21911 iec-q te u-interface psb 4600 pita eeprom psb 4596 alis-d spi data/control interface pci bus psb 4595 alis-a a/b
psb 4600 applications realized with the pita semiconductor group 2-3 preliminary data sheet 12.98 ________________________________________ isdn modem using the isar 34 with two interfaces ________________________________________ psb 4600 pita eeprom spi pci bus psb 7115 isar34 iom-2 peb 2081 sbcx s-interface microcontroller bus psb 21911 iec-q te u-interface
psb 4600 construction of the pita semiconductor group 3-1 preliminary data sheet 12.98 3 construction of the pita ________________________________________ overview the pita provides a peripheral component interconnect (pci) bus interface which acts as a bridge between the pci bus and the different controllers and interfaces: ? the parallel interface control supports up to three external devices. ? the serial interface is controlled by the internal dma controller; serial communications use transmit and receive fifos. ? the eeprom for configuration of the pita and customer specific data storage. ? the general purpose i/o interface. ________________________________________ block diagram of the pita ________________________________________ pita pci controller eeprom control parallel interface control serial interface control dma controller tx fifo rx fifo spi- interface parallel microcontroller interface general purpose interface serial interface pci-bus
psb 4600 construction of the pita semiconductor group 3-2 preliminary data sheet 12.98 ________________________________________ description of the single blocks name provides supports notes pci bus control ? a 32 bit interface at speeds up to 33 mhz ? bus master dma capability for data passing through the serial interface ? target capability for data passing through the parallel interface the power management states: default ?d0 ?d1 ?d3 configurable ?d2 parallel interface control chips with a siemens/intel standard parallel interface, including: ? isdn devices ? modems dsps ? industrial devices serial interface control chips with a serial interface, including: ? analog voice codecs ? analog modem codecs ? iom-2 devices. transmit and receive data are held in separate 16- word fifos.
psb 4600 construction of the pita semiconductor group 3-3 preliminary data sheet 12.98 ________________________________________ eeprom control ? additional information, such as C the subsystem id C the subsystem vendor id C enabling of the d2 power management state this is an optional feature that can be used to customize the pita configuration at start-up. general purpose i/o interface ? gp outputs ?gp inputs ? gp interrupt inputs it can be configured to act as ? input pins ? output pins ? interrupt pins. at start-up these pins are used for the eeprom interface. description of the single blocks name provides supports notes
psb 4600 construction of the pita semiconductor group 3-4 preliminary data sheet 12.98 ________________________________________ logical symbol of the pita ________________________________________ eeprom interface general purpose interface serial interface +5 v 0 v ad(31:0) c/be#(3:0) par frame# trdy# irdy# stop# devsel# idsel perr# serr# req# gnt# clk rst# inta# pme# clkrun# srst# fsc dcl rxd txd gp3 gp2 / eeprom sck gp1 / eeprom si gp0 / eeprom so prst cs#(2:0) pad(7:0) pa(7:0) ale wr# rd# int0# int1 eld ecs# vdd5 vss pci interface parallel microcontroller interface vdd3 +3.3 v
psb 4600 communication with the pita semiconductor group 4-1 preliminary data sheet 12.98 4 communication with the pita ________________________________________ ________________________________________ for communication with the pita following blocks are used: components page pci configuration space 4-2 pci master target controller 4-13 power management 4-13 interrupt control register - retry counter 4-35
psb 4600 communication with the pita semiconductor group 4-2 preliminary data sheet 12.98 4.1 pci configuration space ________________________________________ ________________________________________ overview overview page information about the pci configuration space 4-3 access to the pci configuration space 4-6 base address register 4-7 other registers of the pci configuration space 4-11
psb 4600 communication with the pita semiconductor group 4-3 preliminary data sheet 12.98 4.1.1 information about the pci configuration space ________________________________________ description the pci configuration space contains information about ? the pci device ? the requested address space in the memory space of the pci system. the address space includes 64 32-bit registers where as the first 16 registers build the configuration space header (00h-3ch, refer to configuration space register of the pita on page 10-1) ________________________________________
psb 4600 communication with the pita semiconductor group 4-4 preliminary data sheet 12.98 ________________________________________ construction of the pci configuration space ________________________________________ device id 31 23 15 7 vendor id status command class code revision id bist header type latency timer cach line size base address register 0 (internal registers, asr) base address register 1 (parallel interface -> cs2-0) base address register 2 (unused) base address register 3 (unused) base address register 4 (unused) base address register 5 (unused) cardbus cis pointer subsystem id subsystem vendor id expansion rom base address reserved cap_ptr reserved max_lat min_gnt interrupt pin interrupt line power management capabilities capability id next item pointer pmcsr bridge support data power data register 1 power data register 2 power data register 3 unused configuration space registers unused configuration space registers shaded fields loaded during initialization if eeprom is connected 58h 54h 50h 4ch 48h 44h 40h 3ch 38h 34h 30h 2ch 28h 24h 20h 1ch 18h 14h 10h 0ch 08h 04h 00h 0 8 16 24 cardbus cis 5ch
psb 4600 communication with the pita semiconductor group 4-5 preliminary data sheet 12.98 ________________________________________ ________________________________________ description of register types type description r ? read only ? these bits are initialized by pinstrapping during pci reset h?read only ? hardwired rc ? read clear ? these bits are set by the internal logic ? these bits can be read out and reset by writing logical 1 to them ? writing logical 0 doesnt influence the states of these bits rw ? read write ? these bits can be read out and written via the pci bus ew ? eeprom write ? these bits can be set by an external eeprom after a system reset
psb 4600 communication with the pita semiconductor group 4-6 preliminary data sheet 12.98 4.1.2 access to the pci configuration space ________________________________________ description the pita supports single 32 bit data transactions for the access to the pci configuration space. ________________________________________ ________________________________________ special qualities name description subsystem id ? during system reset: C as well as part of the subsystem vendor id C can be set via pinstrapping if no eeprom is used ? with external eeprom the complete 16 bit value can be loaded for the subsystem id subsystem vendor id ? 16 bit id of the card manufacturer ? default value: 110ah (vendor id of siemens ag) ? identifies the card of the card manufacturer ? has to be applied for at the pci special interest group ? during system reset part of the subsystem id cardbus cis pointer is not supported by the pita, although it is implemented in the pci configuration space
psb 4600 communication with the pita semiconductor group 4-7 preliminary data sheet 12.98 4.1.3 base address register ________________________________________ ________________________________________ ________________________________________ base address registers 0 - 5 base address register description base address register 0 ? the lower 12 bits are connected to logical 0 ? occupies an address space of 4k base address register 1 ? the lower 12 bits are connected to logical 0 ? allows continuous read and write operations for access to the parallel interface ? occupies an address space of 4k C address space is segmented in 4x1k address blocks base address register 2 - 5 not used structure of the address space of base address register 1 address space access to 3ffh - 000h device 1 on the parallel interface (cs0 ) 7ffh - 400h device 2 on the parallel interface (cs1 ) bffh - 800h device 3 on the parallel interface (cs2 ) fffh - c00h not used
psb 4600 communication with the pita semiconductor group 4-8 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ configuration space register: 04h bit 1 memory_access_enable type rw default value 0b description only if this bit is set to 1, the pci interface will react on transactions to the base address registers bar (all base address registers are defined as memory mapped). configuration space register: 10h bit 31:12 base address register 0 type rw default value 0000h bit 11:00 base address register 0 type h default value 000h description bar 0 contains the base address of an address space in the pci main memory through which the internal registers of the pita can be accessed.
psb 4600 communication with the pita semiconductor group 4-9 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ configuration space register: 14h bit 31:12 base address register 1 type rw default value 0000h bit 11:00 base address register 0 type h default value 000h description bar 1 contains the base address of a 4-kbyte address space in the pci main memory through which the internal registers of the pita can be accessed. configuration space register: 18h bit 31:0 base address register 2 type h default value 0000 0000h description base address register 2 is not supported. configuration space register: 1ch bit 31:0 base address register 3 type h default value 0000 0000h description base address register 3 is not supported.
psb 4600 communication with the pita semiconductor group 4-10 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ configuration space register: 20h bit 31:0 base address register 4 type h default value 0000 0000h description base address register 4 is not supported. configuration space register: 24h bit 31:0 base address register 5 type h default value 0000 0000h description base address register 5 is not supported.
psb 4600 communication with the pita semiconductor group 4-11 preliminary data sheet 12.98 4.1.4 other registers of the pci configuration space ________________________________________ ________________________________________ configuration space register: 28h bit 31:0 cardbus cis pointer type h default value 0000 02c0h description bit 31:28 rom_image_number type h default value 0000b description bit 27:3 address_space_offset type h default value 000058h description points to the first cis register in the configuration space. bit 2:0 address_space_indicator type h default value 000b description cis in the device specific configuration space.
psb 4600 communication with the pita semiconductor group 4-12 preliminary data sheet 12.98 ________________________________________ note the cardbus function is not supported in this version of the pita. ________________________________________ ________________________________________ configuration space register: 2ch bit 31:20 subsystem id type h/ew default value 000h bit 19:16 subsystem id type r/ew default value pinstrap value or eeprom value description identifies a specific board of a manufacturer on which the pita is used. the 4 lsbs will be set by pinstrapping during pci reset if no eeprom is used and the complete 16 bit register can be configured by a connected eeprom. bit 15:0 subsystem vendor id type r/ew default value pinstrap value or eeprom value description marks of the vendor of the board on which the pita is used. this register will be set by pinstrapping during pci reset if no eeprom is used or configured from a connected eeprom. this id is allocated by the pci sig.
psb 4600 communication with the pita semiconductor group 4-13 preliminary data sheet 12.98 4.2 pci master target controller ________________________________________ introduction the interface of the pci bus is represented by the pci master/target controller. this controller is part of the pita. the pci master/target controller supports ? several types of transactions, ? two of the six base address registers. the pci master target controller ? has a medium device select behavior, ? truncates burst transactions at the end of the first dataphase. ________________________________________
psb 4600 communication with the pita semiconductor group 4-14 preliminary data sheet 12.98 4.2.1 supported pci commands ________________________________________ ________________________________________ ________________________________________ pci master controller: pci command transaction type memory read single transfer memory write single transfer pci target controller: pci command transaction type memory read single transfer memory read multiple single transfer, mapped on memory read memory read line single transfer, mapped on memory read memory write single transfer memory write and invalidate single transfer, mapped on memory write configuration read single transfer configuration write single transfer
psb 4600 communication with the pita semiconductor group 4-15 preliminary data sheet 12.98 ________________________________________ ________________________________________ note the following timing diagrams are meant as an example and show the transactions to and from the pci configuration space. ________________________________________ overview overview page transaction type single data read 4-16 transaction type single data write 4-17 transaction type burst read 4-18 transaction type burst write 4-20 transaction type fast back to back 4-22
psb 4600 communication with the pita semiconductor group 4-16 preliminary data sheet 12.98 4.2.2 transaction type single data read ________________________________________ timing diagram ________________________________________ adr data 1010 b be 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4600 communication with the pita semiconductor group 4-17 preliminary data sheet 12.98 4.2.3 transaction type single data write ________________________________________ timing diagram ________________________________________ data 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop 1011 b be adr
psb 4600 communication with the pita semiconductor group 4-18 preliminary data sheet 12.98 4.2.4 transaction type burst read ________________________________________ description ? asserting irdy and stop at the first dataphase leads to the disconnection (disconnect-b) of the burst read transaction by the pita. ?stop is asserted until frame is deasserted. ? deassertion of frame means that stop and devsel together are deasserted. ________________________________________ timing diagram ________________________________________ adr data 1010 b be 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4600 communication with the pita semiconductor group 4-19 preliminary data sheet 12.98 ________________________________________ ________________________________________ configuration space register: 04h bit 26:25 devsel_timing type h default value 01b description 01 = medium timing, i.e. the devsel signal will be asserted from the pci interface with the second positive pci clock edge after frame was asserted on the pci bus by a master.
psb 4600 communication with the pita semiconductor group 4-20 preliminary data sheet 12.98 4.2.5 transaction type burst write ________________________________________ description ? asserting irdy and stop at the first dataphase leads to the disconnection (disconnect-b) of the burst write transaction by the pita. ?stop is asserted until frame is deasserted. ? deassertion of frame means that stop and devsel together are deasserted. ________________________________________ timing diagram ________________________________________ adr data1 data2 1010 b be1 be2 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4600 communication with the pita semiconductor group 4-21 preliminary data sheet 12.98 ________________________________________ ________________________________________ configuration space register: 04h bit 26:25 devsel_timing type h default value 01b description 01 = medium timing, i.e. the devsel signal will be asserted from the pci interface with the second positive pci clock edge after frame was asserted on the pci bus by a master.
psb 4600 communication with the pita semiconductor group 4-22 preliminary data sheet 12.98 4.2.6 transaction type fast back to back ________________________________________ description with the fast back to back transaction a pci master controller can perform ? several write transactions ? a read transaction as last transaction without setting the pci bus to idle state in between or releasing the bus to another master. at the end of a transaction: ? the master asserts the frame signal and at the same time the trdy signal is deasserted. the transaction is answered with a retry signal by the pita ? if the parallel interface is included in the fast back to back transaction ?and the parallel interface is still busy. ________________________________________ timing diagram ________________________________________ adr data1 adr2 data2 1011 b be1 1011 b be2 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4600 communication with the pita semiconductor group 4-23 preliminary data sheet 12.98 ________________________________________ ________________________________________ configuration space register: 04h bit 23 fast_back_to_back_capability type h default value 1b description the pita supports fast back-to-back. bit 9 fast_back_to_back_enable type h default value 0b description the pita itself generates no fast back-to-back transactions.
psb 4600 communication with the pita semiconductor group 4-24 preliminary data sheet 12.98 4.3 power management ________________________________________ ________________________________________ overview overview page information about the power management 4-25 configuration space registers of the power management 4-28
psb 4600 communication with the pita semiconductor group 4-25 preliminary data sheet 12.98 4.3.1 information about the power management states ________________________________________ description the pita supports the power management states d0, d1, d2, d3, d3 hot and d3 cold . ________________________________________ d0 ? the d0 state represents the default state of the internal logic after a system reset. ? after a system reset the pci interface is in the d0 state and has to be initialized before being used. ? the pita responds only to configuration accesses while not completely initialized. ? the pci master target controller is disabled while not completely initialized. ________________________________________ d1 ? d1 is a light sleep rate. ? the pita supports the d1 state by default if this state is not disabled by an eeprom configuration. ? the pita pci function can be set to the d1 state by software. ? the pita pci function only responds to pci configuration accesses. ? all accesses to the memory spaces defined by the base address registers are disabled. ? the only pci bus operation the pci interface is allowed to initiate is the assertion of the pme signal. ________________________________________ d2 ? by default the support of the d2 state is disabled in the pita. ? d2 can be enabled by configuration by an eeprom. ? same state behavior as described for the state d1. ________________________________________
psb 4600 communication with the pita semiconductor group 4-26 preliminary data sheet 12.98 ________________________________________ d3 ? same state behavior as described for the state d1. ? the only legal state transitions from d3 to d0 are: C by software reset; the software has to perform a fully reinitialization of the pci function including the pci configuration space. C by system reset ________________________________________ d3 hot ? power and clock are still available to the pita. ? power and clock can be returned to d0 by software. ? state behavior as described for the state d3. ________________________________________ d3 cold (power off) ?d3 cold is a power off state. ? the pci bus power v cc has been disconnected. ? if v cc is removed from the device. ? pme generation is not possible in that state. ________________________________________
psb 4600 communication with the pita semiconductor group 4-27 preliminary data sheet 12.98 ________________________________________ ________________________________________ electrical characteristics parameter symbol limit values unit test condition min max power supply current i cc 0mad3 cold state - power off (power is removed) 19 ma d3 hot state - power down 19 ma d2 state - deep sleep mode 19 ma d1 state - light sleep mode 19 ma d0 state - operational mode
psb 4600 communication with the pita semiconductor group 4-28 preliminary data sheet 12.98 4.3.2 configuration space registers of the power management ________________________________________ ________________________________________ configuration space register: 34h bit 31:8 reserved type h default value 000000h description reserved bit 7:0 cap_ptr type h default value 40h description the capabilities pointer points to the first power management register in the pci configuration space. configuration space register: 40h bit 31:0 power management capabilities (pmc) bit 31 pme_support_d3 cold type h default value 0b description bit 31=pme_support_d3 cold =0; not supported
psb 4600 communication with the pita semiconductor group 4-29 preliminary data sheet 12.98 bit 30 pme_support_d3 hot type h default value 0b description bit 30=pme_support_d3 hot =0; pme supports d3 hot bit 29 pme_support_d2 type h or ew default value 0b description bit 29=pme_support_d2=0; not supported; can be enabled by eeprom bit 28 pme_support_d1 type h or ew default value 1b description bit 28=pme_support_d1=0; not supported; can be enabled by eeprom bit 27 pme_support_d0 type h default value 0b description bit 27=pme_support_d0=0; not supported configuration space register: 40h (contd)
psb 4600 communication with the pita semiconductor group 4-30 preliminary data sheet 12.98 bit 26 d2_support type h or ew default value 0b description ? not supported from the pita by default. ? support can be enabled by eeprom. board with the pita must be able to assert the pme signal. ? d2 state is fully enabled when C assertion of pme_clock C assertion of the pme_support_2 bit is required. bit 25 d1_support type h or ew default value 1b description ? the pita supports the d1 power state by default. ? can be disabled by eeprom. bit 24:22 reserved type h default value 000b description reserved bit 21 dsi (device specific initialization) type h default value 1b description indicates that the pita requires a specific initialization sequence following the transition to d0 state (uninitialized). configuration space register: 40h (contd)
psb 4600 communication with the pita semiconductor group 4-31 preliminary data sheet 12.98 bit 20 reserved type h default value 0b description reserved bit 19 pme_clock type h or ew default value 1b description the pme_clock bit is by default =1, because only pme assertion is supported if the pci clock is present. if also pme assertion out of d2 (no clock running) is supported, the pme_clock bit must be set to 0 by eeprom. bit 18:16 version type h default value 001b description the value 01b indicates that the device complies with the revision 1.0 of the pci power management interface specification. bit 15:8 next_item_ptr type h default value 00h description no next item configuration space register: 40h (contd)
psb 4600 communication with the pita semiconductor group 4-32 preliminary data sheet 12.98 ________________________________________ bit 7:0 capabiltity_id type h default value 01h description indicates that the data structure is currently pointed to the pci power management data structure. configuration space register: 40h (contd) configuration space register: 44h bit 31:24 data_register type h default value 00h description depending on the data_select field (bit 12:9) parts of the power data register (48h) are mapped to this register. bit 23:16 pmcsr_bse (bride support extension) type h default value 00h description not used bit 15 pme_status type rc default value 0b description this bit is set when the pci interface asserts the pme signal independent of the state of the pme_en bit.
psb 4600 communication with the pita semiconductor group 4-33 preliminary data sheet 12.98 bit 15:8 power management control/status register type h default value 00h bit 14:13 data_scale type h default value 00b description depending on the data_select field (bit 12:9) parts of the power_data register are mapped to this register. bit 12:9 data_select type rw default value 0h description ? values from 0 - 7 are supported: parts of the power_data register are mapped to the data register and the data_scale field. ? values from 8 - 15: zero values are mapped to the data register and the data_select field. bit 8 pme_en type rw default value 0b description enables ar disables the pita to assert the pme signal. pme_en=0: assertion of the pme signal is disabled. pme_en=1: the device is enabled to assert the pme signal. configuration space register: 44h (contd)
psb 4600 communication with the pita semiconductor group 4-34 preliminary data sheet 12.98 ________________________________________ bit 8 pme_en type rw default value 000000b description reserved bit 7:2 reserved type h default value 00h description reserved bit 1:0 power_state type rw default value 00b description power_state=00: d0 state (supported by the pita) power_state=01: d1 state (supported by the pita) power_state=10: d2 state (not supported by default) power_state=11: d3 state (supported by the pita). configuration space register: 44h (contd)
psb 4600 communication with the pita semiconductor group 4-35 preliminary data sheet 12.98 4.4 interrupt control register - retry counter ________________________________________ description ? part of the pci master target controller ? functionality: 1. disconnection of the pci master transaction with retry by the addressed pci slave. 2. decrement of the counter. 3. the retry_counter_int bit is set. 4. an interrupt will be generated if the retry_counter_enable bit is set. 5. the pci master starts the transaction again. ________________________________________ ________________________________________ internal register: 00h bit 27 retry_counter_down_int_en type rw default value 0b description enable for the retry_counter_down interrupt bit bit 11 retry_counter_int type rc default value 0b description if a pci master initiated transaction is retried from a pci slave with the number of retries defined in the retry_counter register, this interrupt bit is set by the pci interface.
psb 4600 communication with the pita semiconductor group 4-36 preliminary data sheet 12.98 ________________________________________ ________________________________________ internal register:1ch bit 23:16 retry count register type rw default value 00h description ? part of the pci master target controller ? functionality: 1. disconnection of the pci master transaction with retry by the addressed pci slave. 2. decrement of the counter. 3. the retry_counter_int bit is set. 4. if the retry_counter_enable an interrupt will be generated. 5. the pci master starts the transaction again.
psb 4600 communication with external components semiconductor group 5-1 preliminary data sheet 12.98 5 communication with external components ________________________________________ ________________________________________ interfaces interfaces page serial dma interface 5-2 parallel interface 5-47 general purpose i/o interface 5-65 spi eeprom interface 5-84
psb 4600 communication with external components semiconductor group 5-2 preliminary data sheet 12.98 5.1 serial dma interface ________________________________________ introduction the serial dma interface is used in different modes to transmit and receive 16 bit/ 32 bit data frames. these data frames have different structures: ? data/voice and command ? data/voice and command for two codecs ? different time slots on iom-2. ________________________________________ usage of the serial dma interface the serial dma interface is clocked by default with the internally generated clock (pci clock divided by 40). the ser_clock_set bit must be set in the serial clock select register to 1 when the interface works in alis v3.x or iom-2 mode ? after a system reset ? before starting the dma controller. the reset of this bit can result in an unknown behavior of the fifos and the serial controller. the serial dma interface is fully controlled by the dma controller. ________________________________________
psb 4600 communication with external components semiconductor group 5-3 preliminary data sheet 12.98 ________________________________________ ________________________________________ overview overview page dma controller 5-4 iom-2 mode 1 5-15 iom-2 mode 2 5-18 iom-2 mode 3 5-21 iom-2 modes - supplementary description 5-24 single modem mode v2.1 5-29 single modem mode alis v3.x 5-33 dual modem/modem+voice mode 5-42 loop back mode 5-45
psb 4600 communication with external components semiconductor group 5-4 preliminary data sheet 12.98 5.1.1 dma controller ________________________________________ ________________________________________ overview overview page information about the dma controller 5-5 interrupts 5-9 internal registers of the dma controller 5-10
psb 4600 communication with external components semiconductor group 5-5 preliminary data sheet 12.98 5.1.1.1 information about the dma controller ________________________________________ description for the control of the dma controller, three register are implemented in the internal registers: ? the circular buffer start address is a 4-kbyte aligned pci address which points to a 4-kbyte circular buffer in the pci main memory. all dma read/write transactions between host and pita will be processed via this 4-kbyte address space. ? the dma control register includes the 6-bit parameter dma select which is used to define the mode for the next dma transfer. with the dma_start bit the dma transfer can be started and stopped. ? the contents of the dma write count register is interpreted as a threshold for the write transfers from the dma controller. ________________________________________ ________________________________________ function of the dma controller phase function 1 dma_start bit is set in the dma control register and a dma transfer is started as defined in the dma select register. 2 the dma controller loads the circular buffer start address to its actual circular buffer pointer. 3 the dma controller fills the tx fifo by reading 15 times through the pci interface (pci master mode) from the circular buffer. 4 the dma controller signals the end of the initial sequence. 5 the dma controller increments the actual circular buffer pointer by 4 each read transfer. 6 the dma controller loads the contents of the 12 bit dma write count register to its internal 12 bit dma write counter. 7 after the first 15 read transfers in the beginning of the 16th read transfer the dma controller starts the normal dma algorithm.
psb 4600 communication with external components semiconductor group 5-6 preliminary data sheet 12.98 ________________________________________ ________________________________________ dma write counter after each write transaction from the rx fifo to the buffer the internal dma write counter is incremented by 1. if this counter reaches 0 an interrupt is generated and the counter is loaded again with the contents of the dma write counter register. the internal dma write counter is decremented every two write transactions as long as two 16 bit values per fsc frame are transferred in the following modes: ? 32 bit frame mode ? dual modem mode ? modem+voice mode ? iom-2 mode 2 and 3. ________________________________________ function of the dma algorithm phase function 1 the dma controller reads the 16th data word from the current address in the circular buffer (actual circular buffer pointer) to the internal tx fifo. 2 the dma controller writes the first received 16-bit data word from the rx fifo to the same address in the circular buffer. 3 the dma controller increments the actual buffer pointer by 4. 4 the dma controller reads the 17th data word from the current address in the circular buffer (actual circular buffer pointer) to the internal tx fifo. 5 the dma controller writes the second received 16-bit data word from the rx fifo to the same address in the circular buffer. 6 the dma controller increments the actual buffer pointer by 4. 7and so on
psb 4600 communication with external components semiconductor group 5-7 preliminary data sheet 12.98 ________________________________________ dma_start bit ? the reset of the dma_start bit stops the dma transfer immediately. ? the assertion of the dma_start bit resets the tx and rx fifos. this means that all fifo data is lost when the dma transfer is stopped. ________________________________________ data in the circular buffer since no data is written from the rx fifo to the circular buffer for the first 15 addresses, the first interrupt after the dma_start assertion means that the received data is available in the circular buffer on address ? 003ch to 003ch + [dma write count]: 16 bit frame modes ? 003ch to 0003ch + 2 x [dma write count]: 32 bit frame modes. during normal data transfer every interrupt means that received data is available in the circular buffer on address ? [end address from last interrupt] to [end address from last interrupt] + [dma write count]: 16 bit frame modes ? [end address from last interrupt] to [end address from last interrupt] + 2 x [dma write count]: 32 bit frame modes ________________________________________
psb 4600 communication with external components semiconductor group 5-8 preliminary data sheet 12.98 ________________________________________ example for dma controlled data transfer via circular buffer the status of the dma controller: 16 bit frame access mode (alis v2.1 mode/iom-2 mode 1) when three data frames are already written to the tx line. ________________________________________ rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch rx data 8 rx data 9 rx data 10 rx data 11 rx data 12 rx data 13 rx data 14 rx data 15 rx data 16 rx data 17 rx data 18 rx data 19 rx data 5 rx data 6 rx data 7 rx data 20 tx data 16 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 19 tx data 18 tx data 17 tx data 4 serial control dma controller pita actual_circular_- buffer_pointer tx fifo rx fifo
psb 4600 communication with external components semiconductor group 5-9 preliminary data sheet 12.98 5.1.1.2 interrupts ________________________________________ fifo overflow/empty interrupt ? this interrupt bit is set by the serial controller during the active dma if: C the selected serial protocol could not be generated because there was no data available in the tx fifo. C a received data frame was lost because of fifo overflow. ? this bit is not set during the dma start sequence by the serial controller. ________________________________________ write counter interrupt an interrupt by the write counter must be processed by the host in the following way: ? read out the new received data in the circular buffer ? fill in new transmit data in the circular buffer ? reset the dma_write_counter bit in the interrupt control register. ________________________________________ note this has to be done before the dma write counter expires once again (e.g. interrupt latency), which would cause the generation of a dma_write_counter_overflow. ________________________________________
psb 4600 communication with external components semiconductor group 5-10 preliminary data sheet 12.98 5.1.1.3 internal registers of the dma controller ________________________________________ internal registers: 00h bit 26 fifo_overflow_empty_int_en type rw default value 0b description enable for the fifo_overflow_empty interrupt bit bit 25 dma_write_counter_overflow_int_en type rw default value 0b description enable for the dma_write_counter_overflow interrupt bit. bit 24 dma_write_counter_int_en type rw default value 0b description enable for the dma_write_counter interrupt bit. bit 10 fifo_overflow_empty_int type rc default value 0b description during a dma transfer the serial controller was unable to write received data to the rx fifo because is was already full or the serial controller was unable to send data after the rising fsc edge because of empty tx fifo.
psb 4600 communication with external components semiconductor group 5-11 preliminary data sheet 12.98 ________________________________________ bit 9 dma_write_counter_overflow_int type rc default value 0b description this bit is set if the internal dma write counter is counted down while the dma_write_counter_int bit is still active. this means that the interrupt generated by the dma_write_counter_int bit is not yet processed. bit 8 dma_write_counter_int type rc default value 0b description this bit is set if the number of data, defined in the dma write count register is written through the pci interface. in the 32-bit modes (dual modem, modem+voice, iom-2 mode 2, iom-2 mode 3) this bit is set if the number of data pairs defined in the dma write count register is transferred through the pci interface. internal registers: 00h (contd) internal registers: 04h bit 31:0 dma control register bit 31:9 reserved type h default value 0000000h description reserved
psb 4600 communication with external components semiconductor group 5-12 preliminary data sheet 12.98 ________________________________________ bit 8 dma_start type rw default value 0b description by asserting this bit a dma transfer between the circular buffer and the serial dma interface using internal rx/tx fifos is started. this bit is reset by the host if the dma transfer is to be finished. bit 7:6 reserved type h default value 00b description reserved bit 5:0 dma select type rw default value 000000b description used to define the mode for the next dma transfer: C mode 1 (000001): single modem mode v2.1 C mode 2 (000010): single modem mode v3.x C mode 3 (000100): single dual modem/modem+voice mode v3.x C mode 4 (001000): iom-2 mode 1 C mode 5 (010000): iom-2 mode 2 C mode 6 (100000): iom-2 mode 3 with the dma_start bit the dma transfer can be started or stopped. internal registers: 04h (contd)
psb 4600 communication with external components semiconductor group 5-13 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ internal registers: 08h bit 31:12 circular buffer start address type rw default value 000000h bit 11:0 circular buffer start address type h default value 000h description ? 4-kbyte aligned pci address which points to a 4-kbyte circular buffer in the pci main memory. ? all dma read/write transactions between the host and the pita are processed via this 4-kbyte address space. internal register: 0ch bit 31:02 actual circular buffer pointer type r default value 0000 0000h bit 1:0 actual circular buffer pointer type h default value 00b description by reading this register the software has access to the pci address in the dma circular buffer address pointer. the bits 31-12 are equal the contents of the circular buffer start address register. the bits 11-0 represent the actual dword address in the circular buffer.
psb 4600 communication with external components semiconductor group 5-14 preliminary data sheet 12.98 ________________________________________ ________________________________________ internal register: 1ch bit 11:0 dma write count register type rw default value 000h description
psb 4600 communication with external components semiconductor group 5-15 preliminary data sheet 12.98 5.1.2 iom-2 mode 1 ________________________________________ transmission and reception of data in the circular buffer ________________________________________ dont care b1 31 b2 rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch 15 7 16 8 0 data in circular buffer and on serial dma interface direction data in circular buffer data on serial dma interface transmit bits from circular buffer: [31:16] = dont care [15:8] = b1 [7:0] [7:0] = b2 [7:0] write to serial dma interface: b1 [7:0] b2 [7:0]
psb 4600 communication with external components semiconductor group 5-16 preliminary data sheet 12.98 ________________________________________ timing diagram ________________________________________ ________________________________________ receive bits to circular buffer: [31:16] = dont care [15:8] = b1 [7:0] [7:0] = b2 [7:0] read from serial dma interface: b1 [7:0] b2 [7:0] data in circular buffer and on serial dma interface (contd) direction data in circular buffer data on serial dma interface 8 bit b1 channel du 8 bit b2 channel du 8 bit b1 channel dd 8 bit b2 channel dd 125 us 16 bit b1, b2 frame, double clock fsc (i) dcl (i) txd (o) rxd (i) internal registers: 04h bit 5:0 dma select type rw default value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 4 (001000): iom-2 mode 1 with the dma_start bit the dma transfer can be started or stopped.
psb 4600 communication with external components semiconductor group 5-17 preliminary data sheet 12.98 ________________________________________ ________________________________________ internal register: 20h bit 1 dcl_out_en type rw default value 0b description bit 1=0: the dcl signal is configured as input, i.e. not driven by the pita. bit 0 serial_clock_select type rw default value 0b description bit 0=1: the serial controller is driven with the external dcl input clock.
psb 4600 communication with external components semiconductor group 5-18 preliminary data sheet 12.98 5.1.3 iom-2 mode 2 ________________________________________ transmission and reception of data in the circular buffer ________________________________________ dont care b1 31 b2 rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch 15 7 16 8 0 dont care monitor 0 31 d, c/i, mr, mx 15 7 16 8 0 data in circular buffer and on serial dma interface direction buffer offset data in circular buffer data on serial dma interface transmit 0, 2, 4, ... bits from circular buffer: [31:16] = dont care [15:8] = b1 [7:0] [7:0] = b2 [7:0] write to serial dma interface: b1 [7:0] b2 [7:0]
psb 4600 communication with external components semiconductor group 5-19 preliminary data sheet 12.98 ________________________________________ timing diagram ________________________________________ transmit 1, 3, 5, ... bits from circular buffer: [31:16] = dont care [15:8] = monitor 0 [7:0] [7:0] = d,c/i0,mr,mx [7:0] write to serial dma interface: monitor 0 [7:0] d,c/i0,mr,mx [7:0] receive 0, 2, 4, ... bits to circular buffer: [31:16] = dont care [15:8] = b1 [7:0] [7:0] = b2 [7:0] read from serial dma interface: b1 [7:0] b2 [7:0] 1, 3, 5, ... bits to circular buffer: [31:16] = dont care [15:8] = monitor 0 [7:0] [7:0] = d,c/i0,mr,mx [7:0] read from serial dma interface: monitor 0 [7:0] d,c/i0,mr,mx [7:0] data in circular buffer and on serial dma interface (contd) direction buffer offset data in circular buffer data on serial dma interface 8 bit b1 channel du 8 bit b2 channel du 8 bit b1 channel dd 8 bit b2 channel dd 125 us 16 bit b1, b2 frame, double clock fsc (i) dcl (i) txd (o) rxd (i) 8 bit monitor 0 channel du 8 bit monitor 0 channel dd 2 bit d 2 bit d 4 bit c/i 0 mr mr 4 bit c/i 0 mx mx 16 bit mon0, d, c/i0, mr, mx frame
psb 4600 communication with external components semiconductor group 5-20 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ internal registers: 04h bit 5:0 dma select type rw default value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 5 (010000): iom-2 mode 2 with the dma_start bit the dma transfer can be started or stopped. internal register: 20h bit 1 dcl_out_en type rw default value 0b description bit 1=0: the dcl signal is configured as input, i.e. not driven by the pita. bit 0 serial_clock_select type rw default value 0b description bit 0=1: the serial controller is driven with the external dcl input clock.
psb 4600 communication with external components semiconductor group 5-21 preliminary data sheet 12.98 5.1.4 iom-2 mode 3 ________________________________________ transmission and reception of data in the circular buffer ________________________________________ dont care b1 31 b2 rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch 15 7 16 8 0 dont care ic1 31 ic2 15 7 16 8 0 data in circular buffer and on serial dma interface direction buffer offset data in circular buffer data on serial dma interface transmit 0, 2, 4, ... bits from circular buffer: [31:16] = dont care [15:8] = b1 [7:0] [7:0] = b2 [7:0] bits to serial dma interface: b1 [7:0] b2 [7:0]
psb 4600 communication with external components semiconductor group 5-22 preliminary data sheet 12.98 ________________________________________ timing diagram ________________________________________ transmit 1, 3, 5, ... bits from circular buffer: [31:16] = dont care [15:8] = ic1 [7:0] [7:0] = ic2 [7:0] write to serial dma interface: ic1 [7:0] ic2 [7:0] receive 0, 2, 4, ... bits to circular buffer: [31:16] = dont care [15:8] = b1 [7:0] [7:0] = b2 [7:0] read from serial dma interface: b1 [7:0] b2 [7:0] 1, 3, 5, ... write to circular buffer: [31:16] = dont care [15:8] = ic1 [7:0] [7:0] = ic2 [7:0] read from serial dma interface: ic1 [7:0] ic2 [7:0] data in circular buffer and on serial dma interface (contd) direction buffer offset data in circular buffer data on serial dma interface 8 bit b1 channel du 8 bit b2 channel du 8 bit b1 channel dd 8 bit b2 channel dd 125 us 16 bit b1, b2 frame, double clock fsc (i) dcl (i) txd (o) rxd (i) 8 bit ic1 channel du 8 bit ic1 channel dd 16 bit ic1, ic2 frame 8 bit ic2 channel du 8 bit ic2 channel dd
psb 4600 communication with external components semiconductor group 5-23 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ internal registers: 04h bit 5:0 dma select type rw default value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 6 (100000): iom-2 mode 3 with the dma_start bit the dma transfer can be started or stopped. internal register: 20h bit 1 dcl_out_en type rw default value 0b description bit 1=0: the dcl signal is configured as input, i.e. not driven by the pita. bit 0 serial_clock_select type rw default value 0b description bit 0=1: the serial controller is driven with the external dcl input clock.
psb 4600 communication with external components semiconductor group 5-24 preliminary data sheet 12.98 5.1.5 iom-2 modes - supplementary description ________________________________________ selection of iom-2 time slots the misc register contains four bits. they are used for masking the time slot on iom-2. if bx_msk (x := [1,4]) is set: ? the corresponding value from the tx fifo is not written to the du line. ? ffh is written to this time slot. ? in iom-2 mode 1 the bits b3_msk and b4_msk have no effect. ? data is always transferred from the iom-2 time slot to the rx-fifo. ________________________________________ timing diagram for all iom-2 modes ________________________________________ t fss t fsh t fsw t fsh t :+ t :/ t cyc t iod t iod fsc (i) dcl (i) rxd (i) txd (o) t fss t iih t iis
psb 4600 communication with external components semiconductor group 5-25 preliminary data sheet 12.98 ________________________________________ ________________________________________ figure of the misc register b1 - b4 mask bits ________________________________________ abbreviations for the timing diagram parameter symbol limit values unit min. max. fsc pulse width t fsw 40 ns fsc setup time t fss 40 ns fsc hold time t fsh 40 ns dcl cycle time t cyc 244 ns dcl high time t wh 100 ns dcl low time t wl 100 ns iom output data delay t iod 100 ns iom input data setup t iis 20 ns iom input data hold t iih 20 ns b1 iom-2 mode 1 b2 b1 iom-2 mode 2 b2 monitor 0 d,c/i0,mr,mx b1 iom-2 mode 3 b2 ic1 ic2 misc register: b1_msk b2_msk b3_msk b4_msk
psb 4600 communication with external components semiconductor group 5-26 preliminary data sheet 12.98 ________________________________________ masking of iom-2 time slots (example for iom-2 mode 2) ________________________________________ b1 rxd (i) txd (0) b2 monitor 0 b1 b2 monitor 0 previous iom-2 frame don't care b1 b2 don't care monitor 0 d,c/i0,mr,mx d,c/i0,mr,mx d,c/i0,mr,mx next iom-2 frame mon0 b1 d,c/i0, mr,mx b2 mon0 b1 d,c/i0, mr,mx b2 'ffh' 'ffh' 'ffh' 'ffh' rx fifo tx fifo iom-2 dd line iom-2 du line b1_msk b3_msk b4_msk b2_msk data 1 data 1 data 2 data 2 data 3 data 3 circular buffer memory
psb 4600 communication with external components semiconductor group 5-27 preliminary data sheet 12.98 ________________________________________ internal register: 1ch bit 31:0 misc (miscellaneous register) bit 31 iom_b1_masking type rw default value 0b description bit 31=0: byte b1 is generated out of the circular buffer. bit 31=1: ffh is transmitted on the b1 time slot. bit 30 iom_b3_masking type rw default value 0b description bit 30=0: byte b1 is generated out of the circular buffer. bit 30=1: ffh is transmitted on the b2 time slot. bit 29 iom_monitor_0 / ic1_masking type rw default value 0b description bit 29=0: byte monitor 0 or ic1 is generated out of the circular buffer. bit 29=1: ffh is transmitted on the monitor/ic1 time slot. monitor is used in iom-2 mode 2. ic1 is used in iom-2 mode 3.
psb 4600 communication with external components semiconductor group 5-28 preliminary data sheet 12.98 ________________________________________ bit 28 iom_supl_masking / ic2_masking type rw default value 0b description address:=0: byte d, c/i0, mr, mx or ic2 is generated out of the circular buffer. address:=1: ffh is transmitted on the d, c/i0, mr, mx or ic2 time slot. d, c/i0, mr, mx: used in iom-2 mode 2. ic2: used in iom-2 mode 3 internal register: 1ch (contd)
psb 4600 communication with external components semiconductor group 5-29 preliminary data sheet 12.98 5.1.6 single modem mode v2.1 ________________________________________ ________________________________________ timing diagrams ________________________________________ data in circular buffer and on serial dma interface direction data in circular buffer data on serial dma interface transmit bits from circular buffer: [31:16] = dont care [15:0] = data frame [15:0] write to serial dma interface: data frame [15:0] receive bits to circular buffer: [31:16] = dont care [15:0] = data frame [15:0] read from serial dma interface: data frame [15:0] 16 bit data 16 bit data 125 us 16 bit data frame fsc (i) dcl (o) txd (o) rxd (i) t fsw t dcd t wh t wl t cyc t dci t isu t iho high-z fsc (i) dcl (o) rxd (i) txd (o) t od
psb 4600 communication with external components semiconductor group 5-30 preliminary data sheet 12.98 ________________________________________ ________________________________________ configuration of the single modem mode v2.1 after a system/soft reset ? the configuration of the psb4596 v2.1 in single modem mode is realized by software using the 4-bit general purpose i/o interface of the pita (see general purpose i/o interface on page 5-65.). ? after a system/soft reset the fsc is an input pin both for Cthe pita C the alis v2.1 ? after a system reset the dcl_out_en bit must be set to 1 by the host. ________________________________________ abbreviations for the timing diagram parameter symbol pci clock cycles limit values unit min. typ. max. fsc pulse width t fsw 40 ns dcl delay t dcd 16 480 ns dcl idle time t dci 105 s dcl cycle time t cyc 40 1200 ns dcl high time t wh 20 600 ns dcl low time t wl 20 600 ns dcl duty cycle 45 50 55 % input data setup t isu 10 ns input data hold t iho 10 ns output data delay t od 10 ns
psb 4600 communication with external components semiconductor group 5-31 preliminary data sheet 12.98 ________________________________________ ________________________________________ note a pull down resistor is required on the board to avoid a floating fsc signal in this situation. ________________________________________ ________________________________________ pita configuration for alis v2.1 after a system reset serial dma interface mode ser_clock_sel (clock input to serial dma interface) dcl_out_en (dcl direction) alis v2.1 0 pci clock/ 40 1 dcl output internal registers: 04h bit 5:0 dma select type rw default value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 1 (000001): single modem mode v2.1 with the dma_start bit the dma transfer can be started or stopped.
psb 4600 communication with external components semiconductor group 5-32 preliminary data sheet 12.98 ________________________________________ ________________________________________ internal register: 20h bit 1 dcl_out_en type rw default value 0b description bit 1=1: the dcl signal is output (open drain) and driven by the pita. bit 0 serial_clock_select type rw default value 0b description bit 0=0: the serial controller is driven with the clock signal generated by the internal clock divider.
psb 4600 communication with external components semiconductor group 5-33 preliminary data sheet 12.98 5.1.7 single modem mode alis v3.x ________________________________________ ________________________________________ overview overview page information about the single modem mode alis v3.x 5-34 internal registers of the single modem mode v3.x 5-36
psb 4600 communication with external components semiconductor group 5-34 preliminary data sheet 12.98 5.1.7.1 information about the single modem mode alis v3.x ________________________________________ ________________________________________ timing diagram ________________________________________ data in circular buffers, on serial dma interface direction data in circular buffer data on serial dma interface transmit read from circular buffer: [31:16] = dont care [15:0] = data frame [15:0] write to serial dma interface: data frame [15:0] receive write to circular buffer: [31:16] = dont care [15:0] = data frame [15:0] read from serial dma interface: data frame [15:0] fsc (i) 16 bit data dcl (i) txd (o) 8 bit cmd 8 bit write data 16 bit data 8 bit read data rxd (i) 125 us 32 bit data / command frame
psb 4600 communication with external components semiconductor group 5-35 preliminary data sheet 12.98 ________________________________________ note the timing characteristics of the serial dma interface in single modem mode v3.x mode are identical to the iom-2 modes with the only difference that the dcl signal is not a double bit clock, but a single bit clock, similar to single modem mode v2.1. ________________________________________ configuration of the single modem mode v3.x after a system/soft reset ? realized by starting the dma transfer. C separate from this transfer the command byte and command data byte are written to the alis command registers in the pita on addresses 10h. ? after a system/soft reset the single modem mode v3.x is in the multiplexed mode because the non multiplexed mode is not supported. ________________________________________ ________________________________________ pita configuration for alis v3.x after a system reset serial dma interface mode ser_clock_sel (clock input to serial dma interface dcl_out_en (dcl direction) alis v3.x 1 dcl input clock 0 dcl_out _en 2alis v3.x 1 0 alis v3.x + second codec 10
psb 4600 communication with external components semiconductor group 5-36 preliminary data sheet 12.98 5.1.7.2 internal registers of the single modem mode v3.x ________________________________________ ________________________________________ internal registers: 04h bit 5:0 dma select type rw default value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 2 (000010): single modem mode v3.x with the dma_start bit the dma transfer can be started or stopped. internal register: 10h bit 31:0 alis command register 1 description this command register is used for the first command structure in the fsc time slot by the serial controller. bit 31:25 reserved type h default value 0b description reserved
psb 4600 communication with external components semiconductor group 5-37 preliminary data sheet 12.98 bit 24 new_alis_command_1 type rw default value 0b description bit 24=1: the host has written a new command to the alis command resister 1. bit 24=0: last command written to the alis command register 1 by the host is processed and the received data is available in the alis received data 1 register. this bit is set by software if there is a new command in the alis command 1 register. after the serial dma interface has transmitted the new command and the received data is written to the alis_received_data_1 bits, this bit is reset by the serial dma interface. bit 23:16 alis_received_data_1 type rw default value 00h description during a dma transfer in mode 2 or 3 every time a new command is transferred through the serial dma interface, the received data is fetched and saved in this register. new command means: the command was written through the pci interface to the alis command register. transferring a nop command (ffh or 00h) leads to skipping of the received data. internal register: 10h (contd)
psb 4600 communication with external components semiconductor group 5-38 preliminary data sheet 12.98 ________________________________________ bit 15:8 alis_command_1 type rw default value 00h description during a dma transfer in mode 2 or 3 the contents of this register are transferred as command through the serial dma interface. after transferring the new command through the serial dma interface, the register is set to nop (ffh). bit 7:0 alis_transmit_data_1 type rw default value 00h description during a dma transfer in mode 2 or 3 the contents of this register are transferred as data through the serial dma interface. internal register: 10h (contd)
psb 4600 communication with external components semiconductor group 5-39 preliminary data sheet 12.98 ________________________________________ internal register: 14h bit 31:0 alis command register 2 default value 00000000h bit 31:25 reserved type h default value 000h description reserved bit 24 new_alis_command_2 type rw default value 0b description bit 24=1: the host has written a new command to the alis command 2 register. bit 24=0: last command written to the alis command 2 register by the host is processed and the received data is available in the alis received data 2 register. this bit is set by software if there is a new command in the alis command 2 register. after the serial controller has transmitted the new command and the received data is written in the alis received data 2 register, this bit is reset by the serial controller.
psb 4600 communication with external components semiconductor group 5-40 preliminary data sheet 12.98 ________________________________________ bit 23:16 alis_received_data_2 type rw default value 00h description during a dma transfer in mode 3 every time a new command is transferred through the serial dma interface, the received data is fetched and saved in this register. new command means: the command was written through the pci interface to the alis v3.x command register. if only a nop command (ffh or 00h) is transferred the received data is skipped. bit 15:8 alis_command_2 type rw default value 00h description during a dma transfer in mode 3 the contents of this register are transferred as command through the serial dma interface. after transferring the new command through the serial dma interface, the register is set to nop (ffh). bit 7:0 alis_transmit_data_2 type rw default value 00h description during a dma transfer in mode 3 the contents of this register are transferred as data through the serial interface. internal register: 14h (contd)
psb 4600 communication with external components semiconductor group 5-41 preliminary data sheet 12.98 ________________________________________ ________________________________________ internal register: 20h bit 1 dcl_out_en type rw default value 0b description bit 1=0: the dcl signal is input and driven by the pita. bit 0 serial_clock_select type rw default value 0b description bit 0=1: the serial controller is driven with the external dcl input clock.
psb 4600 communication with external components semiconductor group 5-42 preliminary data sheet 12.98 5.1.8 dual modem/modem+voice mode ________________________________________ description ? the pita transmits and receives two 32 bit frames per fsc time slot. ? each 32 bit frames consists of 16 bit data and 16 bit command/data information. ? for each of the 32 bit frames the 16 bit transmitted data is read out of the tx fifo. ? the 16 bit transmitted data is written to the rx fifo. ? the command read/write data for the first 32 bit frame is read out/written to the alis command register 1 (10h) ? the command read/write data for the second 32 bit frame is read out/written to the alis command register 2 (14h). ? the internal dma write counter is incremented every second write transfer to the circular buffer. ? a new frame transmission starts if the fsc is sampled 1 at a negative edge of the dcl signal. ? the pita starts driving the txd line with the first bit of the transmitted data at the next positive dcl edge. ? during the transmission the rising dcl edge indicates the start of a bit on the txd while the falling edge of the dcl is used to latch the rxd signal. ? the pita stops driving the txd signal with the positive dcl edge when bit 32 of the first or second transmitted frame is on the txd line. ________________________________________
psb 4600 communication with external components semiconductor group 5-43 preliminary data sheet 12.98 ________________________________________ data organization in the circular buffer ________________________________________ timing diagram for the dual modem mode ________________________________________ rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch dont care tx data 1 modem 1 31 15 7 16 8 0 dont care tx data 1 modem 2 31 15 7 16 8 0 16 bit data 8 bit cmd 8 bit write data 16 bit data 8 bit cmd 8 bit write data 16 bit data 8 bit read data 16 bit data 8 bit read data 125 us 32 bit data / command frame 32 bit data / command frame fsc (i) dcl (i) txd (o) rxd (i)
psb 4600 communication with external components semiconductor group 5-44 preliminary data sheet 12.98 ________________________________________ timing diagram for the dual modem+voice mode ________________________________________ description of the timing diagram ? the second 32 bit frame only consists of the 16 bit voice data. ? the voice data is read out the tx fifo. ? the voice data is transmitted through the serial dma interface (msb first). ? during this transmission the received 16 bit voice data (msb first) is written to the rx fifo. ________________________________________ ________________________________________ 16 bit data 8 bit cmd 8 bit write data 16 bit data stuffing pattern 'ffh' 16 bit data 8 bit read data 16 bit data 125 us 32 bit data / command frame 32 bit data frame fsc (i) dcl (i) txd (o) rxd (i) 16 bit stuffing 'ffh' internal registers: 04h bit 5:0 dma select type rw default value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 3 (000100): single dual modem/modem + voice mode v3.x with the dma_start bit the dma transfer can be started or stopped.
psb 4600 communication with external components semiconductor group 5-45 preliminary data sheet 12.98 5.1.9 loop back mode ________________________________________ description if loop_back_mode is set to 1 transmit data is transferred from the tx fifo back to the rx fifo. ________________________________________ mode diagram ________________________________________ pita dma controller tx fifo rx fifo loop closed data 1 data 1 data 2 data 2 data 3 data 3 circular buffer memory serial controller
psb 4600 communication with external components semiconductor group 5-46 preliminary data sheet 12.98 ________________________________________ ________________________________________ internal register: 28h bit 0 loop_back_mode type rw default value 0b description ? bit 0=0: the serial controller transmits and receives data/ commands through the serial dma interface (normal operation mode). ? bit 0=1: the serial controller is in loop back mode. C the serial dma interface reads the data in the transmitting fifo and writes them in the receiving fifo. C no data/command transmission will take place on the serial dma interface. C the serial dma interface is clocked with the defined ser_clock_sel bit.
psb 4600 communication with external components semiconductor group 5-47 preliminary data sheet 12.98 5.2 parallel interface ________________________________________ description the pita has an 8 bit parallel interface to support three external components. this parallel interface is implemented in multiplexed and non multiplexed mode. it works in siemens/intel bus mode. the parallel interface is by default in the non multiplexed mode. ________________________________________ ________________________________________ internal register: 1ch bit 26 parallel_ interface_mode type rw default value 0b description bit 26=0: non multiplexed mode bit 26=1: multiplexed mode bit 24 softreset_parallel_mode type rw default value 0b description bit 24=0: deactivates the reset signal prst to the application. bit 24=1: activates the high active reset signal prst to the application.
psb 4600 communication with external components semiconductor group 5-48 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ mapping between pci data and parallel interface data data on the pci bus ad31-0 pci byte enables c/be3-0 data on the parallel interface data bus pad7-0 ad[31-8] = dont care ad[7-0] = parallel interface data xxx0 pad[7-0] = ad[7-0] ad[31-8] = dont care ad[7-0] = parallel interface data xxx1 no transaction, pci interface disconnects with target abort. address mapping of the 4-kbyte pci address space to the parallel interface address on the pci address bus ad11-0 chip select on the parallel interface address on the parallel interface address bus pad7-0 = ad9-2 (mux mode) pa7-0 = ad9-2 (non-mux mode) 3ffh - 000h cs2-0 = 110 ffh - 00h 7ffh - 400h cs2-0 = 101 ffh - 00h bffh - 800h cs2-0 = 011 ffh - 00h fffh - c00h cs2-0 = 111 (not used)
psb 4600 communication with external components semiconductor group 5-49 preliminary data sheet 12.98 ________________________________________ ________________________________________ modes and timing of the parallel interface modes and timing page ale after system reset 5-50 ale after internal software reset 5-51 ale after setting the parallel interface mode bit 5-52 non multiplexed mode (write transaction) 5-53 non multiplexed mode (read transaction) 5-54 multiplexed mode (write transaction) 5-55 multiplexed mode (read transaction) 5-56 transaction disconnect with target abort 5-57 transaction termination with retry 5-60 timing of the parallel interface 5-62
psb 4600 communication with external components semiconductor group 5-50 preliminary data sheet 12.98 5.2.1 ale after system reset ________________________________________ timing diagram ________________________________________ description both ale and prst are high during rst and remain high for a maximum of 4 cycles after rst goes deasserted. ________________________________________ 12345678910111213 rst prst ale wr rd
psb 4600 communication with external components semiconductor group 5-51 preliminary data sheet 12.98 5.2.2 ale after internal software reset ________________________________________ timing diagram ________________________________________ description ? after the internal soft reset is deasserted the same behavior as in ?ale after system reset generated. ? the soft reset bit in the internal registers can only be set or reset if the parallel interface is in idle state. ? if ale is high before par_rst is asserted, it goes to low one cycle after prst and takes the new value depending on the par_mod bit in the 6 th cycle after prst is deasserted. ________________________________________ prst ale wr rd 12345678910111213
psb 4600 communication with external components semiconductor group 5-52 preliminary data sheet 12.98 5.2.3 ale after setting the parallel interface mode bit ________________________________________ timing diagram ________________________________________ description ? the parallel interface is in non multiplexed mode by default. ? to set the parallel interface into multiplexed mode: the parallel_interface_mode bit has to be set to 1 after reset. ? two pci clocks after finishing this data phase the ale signal is asserted. ________________________________________ 123456789101112 adr data adr1 data cmd1 0000 cmd 0000 ______ frame ____ irdy _____ trdy _______ devsel ad31-0 _______ c/be3-0 _____ stop ale
psb 4600 communication with external components semiconductor group 5-53 preliminary data sheet 12.98 5.2.4 non multiplexed mode (write transaction) ________________________________________ timing diagram ________________________________________ description ? after the address phase on the pci bus (clock3) and the c/be0 =0 verification the address decoding phase of the target (clocks 3 to 4) is active. ? the byte address for the transaction on the parallel interface is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0. ? one pci clock after the pci data phase is finished the data from the pci bus is placed on the data bus pad7-0 (clock 5) and the write transaction starts. ? the data is placed from the pci bus on pad7-0 asserting the wr signal and a cs2-0 signal. ? a new access to the parallel interface could be accepted with an address phase at clock 9. any access before would be cancelled with retry because the pci interface is processing the last access. ________________________________________ adr data cmd xxx0 xxxx pci-adr[9-2] xxxx pci-data[7-0] 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pa7-0 pad7-0
psb 4600 communication with external components semiconductor group 5-54 preliminary data sheet 12.98 5.2.5 non multiplexed mode (read transaction) ________________________________________ timing diagram ________________________________________ description ? after the address phase on the pci bus (clock3) and the c/be0 =0 verification the address decoding phase of the target (clocks 3 to 4) is active. ? the byte address for the transaction on the parallel interface is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0 (clock 5). ? the following pci clock asserts the signals rd and cs2-0. ? after 5 clocks the rd signal is deasserted. ? the data from pad7-0 is fetched. ? with the next clock the data is placed on the pci bus and the data phase is finished by deasserting the trdy signal. ? the 8 bit data from the parallel interface is placed an the last significant byte of the pci data bus ad7-0. ________________________________________ adr data cmd xxx0 xxxx pci-adr[9-2] xxxx data[7-0] 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pa7-0 pad7-0
psb 4600 communication with external components semiconductor group 5-55 preliminary data sheet 12.98 5.2.6 multiplexed mode (write transaction) ________________________________________ timing diagram ________________________________________ description ? after the address phase on the pci bus (clock 3) and the c/be0 =0 verification the address decoding phase of the target (clocks 3 to 4) is active. ? the byte address for the transaction on the parallel interface address is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0. ? one pci clock after the pci data phase is finished the data from the pci bus is placed on the data bus pad7-0 (clock 5) and the write transaction starts. ? the data is placed from the pci bus on pad7-0 asserting the cs2-0 signal. ? the ale signal is deasserted. ? with the following pci clock the data from the pci bus is placed on pad7-0 (clock5). ?the wr signal is asserted. ? a new access to the parallel interface could be accepted with an address phase at clock 11. any access before would be cancelled with retry because the pci interface is processing the last access. ________________________________________ adr data1 cmd xxx0 pci-adr[9-2] pci-data1[7-0] 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4600 communication with external components semiconductor group 5-56 preliminary data sheet 12.98 5.2.7 multiplexed mode (read transaction) ________________________________________ timing diagram ________________________________________ description ? after the address phase on the pci bus (clock 3) and the c/be0 =0 verification the address decoding phase of the target (clocks 3 to 4) is active. ? the byte address for the transaction on the parallel interface is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0 (clock 5). ? the following pci clock asserts the ale signal. ? after 2 clocks the ale signal is deasserted. ? the address is held for one more clock. ? after 5 clocks the rd signal is deasserted. ? at the same time the data is latched in die pci output registers. ? trdy is asserted on the pci bus to finish the data phase. ? at the next clock the cs2-0 and ale signals are deasserted. ________________________________________ $'5 data1 cmd xxx0 pci-adr[9-2] data1[23-16] 1234567891011121314 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4600 communication with external components semiconductor group 5-57 preliminary data sheet 12.98 5.2.8 transaction disconnect with target abort ________________________________________ timing diagram ________________________________________ description c/be0 = 1: no transaction is started on selected parallel interface, due to the wrong byte enable. the pci master target controller disconnects the transaction with target abort. ________________________________________ adr data adr data cmd xxx1 cmd xxx1 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4600 communication with external components semiconductor group 5-58 preliminary data sheet 12.98 ________________________________________ configuration space register: 04h bit 30 system_error_signaled type rc default value 0b description this bit is set by the pitas pci master, if the master asserts the system error signal on the pci bus. this occurs if a transaction initiated by the pita is disconnected with target abort. bit 29 master_abort_detected type rc default value 0b description if no fast/medium/slow or subtractive slave reacts to a pci transaction initiated by the pci master, the master will discard the transaction and set this bit. bit 28 master_abort_detected type rc default value 0b description if a pci transaction initiated by the pci master is disconnected with target abort, the pci master will set this bit. the pci master is not allowed to start a new pci transaction, until this bit is deasserted.
psb 4600 communication with external components semiconductor group 5-59 preliminary data sheet 12.98 ________________________________________ bit 27 target_abort_signaled type rc default value 0b description this bit is set by the pci interface if a transaction was disconnected with target abort. the pita will disconnect transactions with target abort if illegal byte enables are detected. bit 8 system_error_enable type rw default value 0b description if this bit is asserted, the pci master will assert the system error signal (serr ) if it receives a target abort during a transaction initiated by itself. bit 2 master_enable type rw default value 0b description if this bit is set to 0 the pci master is not allowed to start any transaction on the pci bus. configuration space register: 04h (contd)
psb 4600 communication with external components semiconductor group 5-60 preliminary data sheet 12.98 5.2.9 transaction termination with retry ________________________________________ description retry means that the pita finishes a transaction without a data transfer by asserting the signal stop , because the parallel interface processes another transaction. the pci master target controller has to repeat the transaction until a slave accepts the transaction with data transfer or target abort. this sequence is invisible for the software. ________________________________________ timing diagram ________________________________________ adr1 data1 adr2 data2 cmd1 xxx0 cmd2 xxx0 pci-adr[9-2] pci-data1[7-0] 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4600 communication with external components semiconductor group 5-61 preliminary data sheet 12.98 ________________________________________ explanation of adr/cmd and adr2/cmd2 adr/cmd: the pci master target controller accepts the write transaction adr2/cmd2: the second transaction is retried. ________________________________________
psb 4600 communication with external components semiconductor group 5-62 preliminary data sheet 12.98 5.2.10 timing of the parallel interface ________________________________________ read timing ________________________________________ write timing ________________________________________ multiplexed address timing ________________________________________ rd x cs ad0-ad7 t rr t ri t rd t df data wr x cs ad0-ad7 t ww t wi t wd t dw data ale wr x cs or rd x cs ad0-ad7 t aa t al t la t als t ad address
psb 4600 communication with external components semiconductor group 5-63 preliminary data sheet 12.98 ________________________________________ non multiplexed address timing ________________________________________ application reset and interrupt timing ________________________________________ t as t ah address a0-a7 wr x cs or rd x cs valid state prst, srst host write access to the register t rod previous state int1 (i) into (i) t iod inta (o)
psb 4600 communication with external components semiconductor group 5-64 preliminary data sheet 12.98 ________________________________________ ________________________________________ abbreviations of the timing diagrams parameter sym- bol pci clock cycles limit values unit min. max . ale pulse width t aa 5 150 ns address setup time to ale t al 130 ns address hold time from ale t la 130 ns address latch setup time to wr , rd t als 130 ns address setup time t as 130 ns address hold time t ah 130 ns ale guard time t ad 130 ns rd pulse width t rr 5 150 ns data output delay from rd t rd 5 150 ns data float from rd t df 130ns rd control interval t ri 5 150 ns w pulse width t ww 390 ns data setup time to w x cs t dw 260 ns data hold time w x cs t wd 130 ns w control interval t wi 390 ns reset output delay t rod 390ns interrupt output delay t iod 260ns
psb 4600 communication with external components semiconductor group 5-65 preliminary data sheet 12.98 5.3 general purpose i/o interface ________________________________________ ________________________________________ overview overview page information about the gp i/o interface 5-66 timing of the gp i/o interface 5-68 internal registers of the gp i/o interface 5-69 input mode 5-76 output mode 5-78 interrupt mode 5-80 usage of the gp i/o interface as alis v2.1 control interface 5-82
psb 4600 communication with external components semiconductor group 5-66 preliminary data sheet 12.98 5.3.1 information about the gp i/o interface ________________________________________ description for additional access to external devices with a slow interface behavior a 4 bit general purpose i/o interface is implemented in the pita. ________________________________________ ________________________________________ application interrupt ? the pci interface supports 2 separate interrupt inputs. ? four pins of the general purpose i/o interface can be used as additional interrupt inputs. ? each of these 6 interrupts has an interrupt_enable bit and an interrupt_control_status bit. ? for the two separate inputs (int0 and int1) the enable bit is located in the interrupt control register. ? for the general purpose i/o the enable bit is located in the interface control register. ________________________________________ pinning pin pin name general purpose i/o function spi eeprom function 2 gp0 i/o/int. so 3 gp1 i/o/int. si 4 gp2 i/o/int. sck 5 gp3 i/o/int. C
psb 4600 communication with external components semiconductor group 5-67 preliminary data sheet 12.98 ________________________________________ ________________________________________ control registers for gpx pins register register bit description interrupt control register - icr gpx_int gp interrupt status gp i/o interface control register gpx_int_en gp interrupt enable gpx_out_en gp output enable gpx_out gp output value gpx_in gp input value
psb 4600 communication with external components semiconductor group 5-68 preliminary data sheet 12.98 5.3.2 timing of the gp i/o interface ________________________________________ timing diagram ________________________________________ t od valid state host write access gp0-3 (o) gpx configured as output t isu t iho valid state host read access gp0-3 (i) gpx configured as input t iod gpx configured as interrupt input gp0-3 (i) inta (o) abbreviations of the timing diagram parameter symbol limit values unit min. max. gpx output data delay t od 90 ns gpx input data setup t isu 30 ns gpx input data hold t iho 30 ns gpx interrupt output delay t iod 90 ns
psb 4600 communication with external components semiconductor group 5-69 preliminary data sheet 12.98 5.3.3 internal registers of the gp i/o interface ________________________________________ internal register: 00h bit 5 gp3_int type rc default value 0b description the gp3 pin can be used as active low interrupt input if gp3_int_en=1 and gp3_out_en=0. the bit is set to 1 if both are true and low is detected at this pin. bit 4 gp2_int type rc default value 0b description the gp2 pin can be used as active low interrupt input if gp2_int_en=1 and gp2_out_en=0. the bit is set to 1 if both are true and low is detected at this pin. bit 3 gp1_int type rc default value 0b description the gp1 pin can be used as active low interrupt input if gp1_int_en=1 and gp1_out_en=0.
psb 4600 communication with external components semiconductor group 5-70 preliminary data sheet 12.98 ________________________________________ bit 2 gp0_int type rc default value 0b description the gp0 pin can be used as active low interrupt input if gp0_int_en=1 and gp0_out_en=0. internal register: 00h (contd) internal register: 18h bit 31:0 gp i/o interface control register type 00000000h bit 31:28 reserved type h default value 0h description reserved bit 27 gp3_int_en type rw default value 0b description bit 27=1: gp3 is configured as input, the pin is used as an interrupt input with gp3_int_en as corresponding bit in the interrupt control register. bit 27=1: gp3 is not used as an interrupt pin.
psb 4600 communication with external components semiconductor group 5-71 preliminary data sheet 12.98 bit 26 gp2_int_en type rw default value 0b description bit 26=1: gp2 is configured as input, the pin is used as an interrupt input with gp2_int_en as corresponding bit in the interrupt control register. bit 26=0: gp2 is not used as an interrupt pin. bit 25 gp1_int_en type rw default value 0b description bit 25=1: gp1 is configured as input, the pin is used as an interrupt input with gp1_int_en as corresponding bit in the interrupt control register. bit 25=0: gp1 is not used as an interrupt pin. bit 24 gp0_int_en type rw default value 0b description bit 24=1: gp0 is configured as input, the pin is used as an interrupt input with gp0_int_en as corresponding bit in the interrupt control register. bit 24=0: gp0 is not used as an interrupt pin. internal register: 18h (contd)
psb 4600 communication with external components semiconductor group 5-72 preliminary data sheet 12.98 bit 23:20 reserved type h default value 000b description reserved bit 19 gp3_out_en type rw default value 0b description bit 19=1: gp_3 is configured as output pin. bit 19=0: gp_3 is configured as input pin. bit 18 gp2_out_en type rw default value 0b description bit 18=1: gp_2 is configured as output pin. bit 18=0: gp_2 is configured as input pin. bit 17 gp1_out_en type rw default value 0b description bit 17=1: gp_1 is configured as output pin. bit 17=0: gp_1 is configured as input pin. internal register: 18h (contd)
psb 4600 communication with external components semiconductor group 5-73 preliminary data sheet 12.98 bit 16 gp0_out_en type rw default value 0b description bit 16=1: gp_0 is configured as output pin. bit 16=0: gp_0 is configured as input pin. bit 15:12 reserved type h default value 000b description reserved bit 11 gp3_in type r default value 0b description actual value on the gp3 pin (pin feedback) bit 10 gp2_in type r default value 0b description actual value on the gp2 pin (pin feedback) internal register: 18h (contd)
psb 4600 communication with external components semiconductor group 5-74 preliminary data sheet 12.98 bit 9 gp1_in type r default value 0b description actual value on the gp1 pin (pin feedback) bit 8 gp0_in type r default value 0b description actual value on the gp0 pin (pin feedback) bit 7:4 reserved type h default value 0000b description reserved bit 3 gp3_out type rw default value 0b description the gp3 pin is driven with the value written to this output register if the gp3_out_en is set to 1. internal register: 18h (contd)
psb 4600 communication with external components semiconductor group 5-75 preliminary data sheet 12.98 ________________________________________ bit 2 gp2_out type rw default value 0b description the gp2 pin is driven with the value written to this output register if the gp2_out_en is set to 1. bit 1 gp1_out type rw default value 0b description the gp1 pin is driven with the value written to this output register if the gp1_out_en is set to 1. bit 0 gp0_out type rw default value 0b description the gp0 pin is driven with the value written to this output register if the gp0_out_en is set to 1. internal register: 18h (contd)
psb 4600 communication with external components semiconductor group 5-76 preliminary data sheet 12.98 5.3.4 input mode ________________________________________ description for using a general purpose i/o pin as input pin, the control register must be configured as follows: gpx_out_en = 0 (output disabled) gpx_int_en = 0 (interrupt disabled) (x := [0, 3]) description of the internal register 18h on page 5-70. the gpx_out and gpx_int bits can be treated as dont care in this mode. the current signal value at the pin gpx can be read from register bit gpx_in. ________________________________________ internal structure of a gpx input pin ________________________________________ timing diagram ________________________________________ d q q gpx_in gpx t isu t iho valid state host read access gp0-3 (i) gpx configured as input
psb 4600 communication with external components semiconductor group 5-77 preliminary data sheet 12.98 ________________________________________ ________________________________________ abbreviations of the timing diagram parameter symbol limit values unit min. max. gpx input data setup t isu 30 ns gpx input data hold t iho 30 ns
psb 4600 communication with external components semiconductor group 5-78 preliminary data sheet 12.98 5.3.5 output mode ________________________________________ description for using a general purpose i/o pin as output pin, the control register must be configured as follows: gpx_out_en = 1 (output enabled) gpx_int_en = dont care (x := [0, 3]) description of the internal register 18h on page 5-70. the gpx_in and gpx_int register bits can be treated as dont care in this mode. the gpx pin will drive the connected signal line with the value defined in the gpx_out register bit, which is programmed by the host. ________________________________________ internal structure of a gpx output pin ________________________________________ d q q gpx_out en gpx d q q gpx_out_en
psb 4600 communication with external components semiconductor group 5-79 preliminary data sheet 12.98 ________________________________________ timing diagram ________________________________________ ________________________________________ t od valid state host write access gp0-3 (o) gpx configured as output abbreviation of the timing diagram parameter symbol limit values unit min. max. gpx output data delay t od 90 ns
psb 4600 communication with external components semiconductor group 5-80 preliminary data sheet 12.98 5.3.6 interrupt mode ________________________________________ description for using a general purpose i/o pin as output pin, the control register must be configured as follows: gpx_out_en = 1 (output disabled) gpx_int_en = 1 (interrupt enabled) (x := [0, 3]) description of the internal register 18h on page 5-70. the gpx_out register bit can be treated as dont care in this mode. the gpx pin acts as an active low interrupt input pin. if the device detects 0 at the gpx pin ? the gpx_int register is set to 1 ? an interrupt on the pci bus is generated ? the current state of the gpx pin can be read from gpx_in bit or can be treated as dont care. ________________________________________ internal structure of a gpx interrupt input pin ________________________________________ timing diagram ________________________________________ d q q gpx_in gpx >=1 1 4 3 x 0 inta t iod gpx configured as interrupt input gp0-3 (i) inta (o)
psb 4600 communication with external components semiconductor group 5-81 preliminary data sheet 12.98 ________________________________________ ________________________________________ abbreviation of the timing diagram parameter symbol limit values unit min. max. gpx interrupt output delay t iod 90 ns
psb 4600 communication with external components semiconductor group 5-82 preliminary data sheet 12.98 5.3.7 usage of the gp i/o interface as alis v2.1 control interface ________________________________________ the serial control interface of the alis v2.1 can be realized by software using the general purpose i/o pins. the gp3 pin is used as cs pin while the other three gpx pins are shared with the spi eeprom interface. the gp3 pin is driven high during the automatic eeprom configuration phase after a system reset to disable the alis v2.1 control interface. pin description on page 7-7. ________________________________________ ________________________________________ description pita signals alis signals description gp3 out cs chip select (active low), for enabling the psb4596 control interface. gp2 out dclk clock signal for the control interface. (psb4596 accepts 1 khz to 1024 khz) gp1 in dout data input for pita, data output from psb4596. data input is latched at the negative dclk edge. gp0 out din data output from pita, data input for psb4596. data output changes with the rising dclk edge. int1 in int interrupt signal (high active) srst out reset reset signal (low active)
psb 4600 communication with external components semiconductor group 5-83 preliminary data sheet 12.98 ________________________________________ timing diagram for a write transaction with two data bytes transmitted ________________________________________ timing diagram for a read access with one data byte received via dout ________________________________________ gp3 (o) / cs (i) gp2 (o) / dclk (i) gp1 (i) / dout (o) gp0 (o) / din (i) high `z control data byte 1 data byte 2 control frame 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 gp3 (o) / cs (i) gp2 (o) / dclk (i) gp1 (i) / dout (o) gp0 (o) / din (i) high `z control identification data byte 1 control frame 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 high `z
psb 4600 communication with external components semiconductor group 5-84 preliminary data sheet 12.98 5.4 spi eeprom interface ________________________________________ ________________________________________ overview overview page information about the spi eeprom interface 5-85 timing of the spi eeprom interface 5-88 internal registers for the spi eeprom interface 5-90
psb 4600 communication with external components semiconductor group 5-85 preliminary data sheet 12.98 5.4.1 information about the spi eeprom interface ________________________________________ description three pins are used to provide an spi tm -compatible serial interface to a 256 x 8 bit eeprom. these pins also do double-duty as part of the general purpose interface. two other pins are also used to select the eeprom chip and to enable/ disable the automatic reconfiguration of the configuration space by the eeprom. this would occur after a system reset. the eeprom can be used for: ? automatic reconfiguration of the pita. ? customer specific purposes (e.g. storage of serial board numbers). ________________________________________ automatic reconfiguration of the pita parts of the pci configuration space can be configured with data from this external eeprom after system reset. the following sequence is processed by the pita: ? the pita checks: C whether the eld (eeprom_load) pin is clamped to 1. C whether the first byte in the eeprom (address location 00h) is aah. ? if the first step was successful, the pita starts: C reading out four bytes starting with address 01h. C writing the read values in the configuration space address 00h. C reading out the next four bytes. C writing the read values in the configuration space address 04h. C and so on. ________________________________________ note during the configuration phase, all access to the pci interface are answered with retry by the pita. ________________________________________
psb 4600 communication with external components semiconductor group 5-86 preliminary data sheet 12.98 ________________________________________ using the eeprom for customer specific purposes the contents of the eeprom can be programmed by writing a command to the eeprom control register and initiating a read/write transaction to the eeprom. ________________________________________ note if the automatic reconfiguration of the pita is used (eld pin clamped to 1), only those addresses in the eeprom not mapped to the pci configuration space should be used. ________________________________________ starting a read or write transaction the contents of the eeprom can be programmed by writing a command to the eeprom control register and initiating a read/write transaction to the eeprom. ? the host writes C the eeprom command value before the next eeprom transfer is started. C the eeprom byte address value for read or write access. C the eeprom data value for the write status register and write data to memory array. ? the host sets the eeprom_start bit. ? if the eeprom interface detects the asserted eeprom_start bit; it C interprets the eeprom command. ? starts the read or write transaction to the connected eeprom. ? if the transactions are started via the eeprom control register, then the eeprom interface does not check for a connected eeprom. ________________________________________
psb 4600 communication with external components semiconductor group 5-87 preliminary data sheet 12.98 ________________________________________ after finishing the transaction: ? the eeprom control module: C deasserts the eeprom_start bit. C generates an interrupt in the eeprom control int register, if the eeprom_control_int_en bit is set to 1. ? if the eeprom command register is set to rdsr or read, then the value of the eeprom is available in the eeprom data register. ________________________________________ connection of an alis v2.1 device to the serial control interface for the connection of an alis v2.1 device to the serial control interface of the pita the gp3 pin is additionally used as low active chip select signal cs to the alis v2.1. the gp3 pin is always driven high and therefore the alis v2.1 interface is inactive during the phase of automatic initialization of the pci configuration space. ________________________________________
psb 4600 communication with external components semiconductor group 5-88 preliminary data sheet 12.98 5.4.2 timing of the spi eeprom interface ________________________________________ timing diagram ________________________________________ t css t cyc t clh t cll t isu t iho t csi t csh t or t of t osu t oho t od lsb out lsb in high-z epcs (o) sck (o) so (i) si (o) abbreviations of the timing diagram parameter symbol limit values unit min. max. chip select setup time t css 500 ns chip select hold time t csh 500 ns chip select inactive t csi 500 ns clock cycle time t cyc 1000 ns clock high time t clh 410 ns clock low time t cll 410 ns clock output rise time t or 2 s clock output fall time t of 2s input data setup time t isu 100 ns input data hold time t iho 100 ns output data setup time t osu 500 ns
psb 4600 communication with external components semiconductor group 5-89 preliminary data sheet 12.98 ________________________________________ note the sck is a strobed clock signal (i.e. it is only active as long as valid data is transferred on si/so line) and output data is written on the falling edge and input data is latched on the rising edge. although the first sck edge is positive, the pita drives the first valid bit on si (output) with the falling edge of epcs , so the minimum setup time with respect to the first sck rising edge is guaranteed. ________________________________________ output data hold time t oho 0 500 ns output disable time t od 500 ns write cycle time t wc 10 ms abbreviations of the timing diagram (contd) parameter symbol limit values unit min. max.
psb 4600 communication with external components semiconductor group 5-90 preliminary data sheet 12.98 5.4.3 internal registers for the spi eeprom interface ________________________________________ ________________________________________ internal register: 00h bit 28 eeprom_control_int_en type rw default value 0b description enable for the eeprom_control_int interrupt bit bit 12 eeprom_control_int type rc default value 0b description the eeprom_control_int_en bit and the eeprom are set to 1 if the transaction is finished. internal register: 24h bit 31:0 eeprom control register default value 00000000h bit 31:25 reserved type h default value 0000h description reserved
psb 4600 communication with external components semiconductor group 5-91 preliminary data sheet 12.98 bit 24 eeprom_start type rw default value 0b description bit 24=1: an eeprom transaction is started with the eeprom command, eeprom data and eeprom byte address. bit 24=0: an eeprom transaction can be started. bit 23:16 eeprom command type rw default value 00h description the following spi commands are supported: 00000110: wren set write enable latch 00000100: wrdi reset write enable latch 00000101: rdsr read status register 00000001: wrsr write status register 00000011: read read data from memory array 00000010: write write data to memory array others: no action bit 15:8 eeprom byte address type rw default value 00h description byte address for the next eeprom read or write transaction. internal register: 24h (contd)
psb 4600 communication with external components semiconductor group 5-92 preliminary data sheet 12.98 ________________________________________ bit 7:0 eeprom data type rw default value 00h description ? transaction with a read command: after the transaction has been finished this register contains the byte that has been read from the eeprom. ? transaction with a write command: the contents of this register will be written to the eeprom byte address if the connected eeprom after the eeprom_start bit is set. internal register: 24h (contd)
psb 4600 configuration of the pita semiconductor group 6-1 preliminary data sheet 12.98 6 configuration of the pita ________________________________________ pinstrapping pinstrapping is used for: ? loading the subsystem vendor id. ? loading the least significant 4 bits of the subsystem id to the pci configuration space. several output pins from the parallel microcontroller interface and the general purpose i/o interface are implemented as tristate output pins. during pci reset they are driven in tristate mode and the external logic value is latched in the subsystem id (4 lsbs) and the subsystem vendor id. this means that the signals on board, connected to these pins, must be forced with pullup/ pulldown resistors to the desired value if they are not driven by the pita. ________________________________________ ________________________________________ automatic reconfiguration of the pita with the serial eeprom the pita can also be configured by the eeprom after system reset. pinstrap values are overwritten by this process if the procedure described in automatic reconfiguration of the pita on page 85 was successful. ________________________________________ pins used for pinstrapping during pci reset signal name usage during pci reset (pinstrapping) i/o pad(7:0) subsystem vendor id(15:8) io pa(7:0) subsystem vendor id(7:0) ots gp3 subsystem id(3) io gp2 subsystem id(2) io gp1 subsystem id(1) io gp0 subsystem id(0) io
psb 4600 pinning semiconductor group 7-1 preliminary data sheet 12.98 7pinning ________________________________________ pita pinout this illustration shows the numbered pins and their respective signals: ________________________________________ pita t-qfp-100-1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 cs1 cs2 inta vdd3 vss vdd5 vdd3 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 c/be0 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 c/be1 par serr perr stop devsel trdy irdy frame c/be2 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 prst pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 rd cs0 wr vdd3 vss vdd5 ale int0 srst dcl rxd txd fsc int1 eld ecs gp3 test gp2 gp1 gp0 clkrun pme rst clk gnt req vdd3 vss vdd5 vdd3 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 idsel
psb 4600 pinning semiconductor group 7-2 preliminary data sheet 12.98 ________________________________________ overview the following table lists the interfaces and their respective pins: ________________________________________ ________________________________________ interface total in out i/o page pci bus 52 4 5 43 7-3 parallel interface 23 3 14 8 7-4 serial interface 5 2 2 1 7-6 gp i/o interface 4 0 0 4 7-7 special eeprom signals 211 0 7-8 test if 1 1 0 7-8 power supply 11 11 0 7-8 total 100 11 22 (+11 power supply) 56 - description of pin types type description o output pin i input pin io bidirectional input/output pin (od) open drain
psb 4600 pinning semiconductor group 7-3 preliminary data sheet 12.98 ________________________________________ this table lists the pins characteristics of the pci bus pin no. signal name pin count type function 9 clk 1 i pci - clock (max. 33 mhz) 8rst 1 i pci - reset 16 - 23, 26 - 33, 44 - 51, 53 - 60 ad(31:0) 32 io pci - address-/data bus 24, 34, 43, 52 c/be (3:0) 4 io pci - command/byte enable bus (byte enables are low active) 42 par 1 io pci - parity 65 inta 1 od pci - interrupt signal 25 idsel 1 i pci - initialization device select signal for cardbus boards this signal must set to 1 35 frame 1 io pci - frame 36 irdy 1 io pci - initiator ready 37 trdy 1 io pci -target ready 38 devsel 1 io pci - device select 39 stop 1 io pci - stop 11 req 1 ots pci - bus request 10 gnt 1 i pci - bus grant
psb 4600 pinning semiconductor group 7-4 preliminary data sheet 12.98 ________________________________________ 40 perr 1 io pci - parity error 41 serr 1 od pci - system error 7pme 1 od pci - power management event 6clkrun 1 i clock run this table lists the pins characteristics of the pci bus (contd) pin no. signal name pin count type function this table lists the pins characteristics of the parallel interfaces pin no. signal name pin count type function 76 prst 1 o active high reset 66, 67, 87 cs (2:0) 3 o chip select signals for three devices connected to the parallel microcontroller interface. 84 - 77 pad(7:0) 8 io - multiplexed bus mode: address/data bus for the parallel interface. - non-multiplexed bus mode: data bus for the parallel interface.
psb 4600 pinning semiconductor group 7-5 preliminary data sheet 12.98 ________________________________________ 75 - 68 pa(7:0) 8 ots - multiplexed bus mode: not used; pins can be left not connected. - non-multiplexed bus mode: address bus for the parallel interface. 91 ale 1 o address latch enable signal, active high. in non-multiplexed mode the ale input of peripheral devices must be connected to vss. 86 wr 1 o write signal, active low 85 rd 1 o read signal, active low 92 int0 1 i standard active low interrupt input for connected devices, which is forwarded to the pci interface (inta ). 98 int1 1 i standard active high interrupt input for connected devices, which is forwarded to the pci interface (inta ). this table lists the pins characteristics of the parallel interfaces (contd) pin no. signal name pin count type function
psb 4600 pinning semiconductor group 7-6 preliminary data sheet 12.98 ________________________________________ ________________________________________ this table list the pins characteristics of the serial interface pin no. signal name pin count type function 93 srst 1 o active low reset output. 97 fsc 1 i frame synchronisation clock signal, 8 khz. 94 dcl 1 i o (od) serial data clock signal. the direction of this pin can be controlled by the dcl_out_en bit in the internal registers. by default this pin is input. for psb4596 v2.1 mode, this pin must configured as output (open drain), for all other modes this pin must be input. 95 rxd 1 i serial data input signal 96 txd 1 o (od) serial data output signal
psb 4600 pinning semiconductor group 7-7 preliminary data sheet 12.98 ________________________________________ ________________________________________ this table lists the pins characteristics of the general purpose i/o interface pin no. signal name pin count type function 2 gp3 1 io general purpose i/o pin 3 this pin is driven high during the automatic eeprom configuration if eld = 1. 3 gp2 1 io general purpose i/o pin 2 serial eeprom interface : sck - serial clock signal. 4 gp1 1 io general purpose i/o pin 1 serial eeprom interface : so - serial data output from eeprom (input to the pita). 5 gp0 1 io general purpose i/o pin 0 serial eeprom interface : si - serial data input to the eeprom (output from the pita).
psb 4600 pinning semiconductor group 7-8 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ this table lists the pins characteristics of the special eeprom signals pin no. signal name pin count type function 99 eld 1 i eeprom load 1 -> eeprom configuration is enabled. 0 -> eeprom configuration is disabled. 100 ecs 1 o eeprom chip select (spi signal) this table lists the pins characteristics of the test if pin no. signal name pin count type function 1 test 1 i test input
psb 4600 pinning semiconductor group 7-9 preliminary data sheet 12.98 ________________________________________ ________________________________________ this table lists the pins characteristics of the power supply pin no. signal name pin count type function 12, 15, 61, 64, 88 vdd3 5 i positive power supply 3.3v 10% 14, 62, 90 vdd5 3 i positive power supply 5v 10% 13, 63, 89 vss 3 i ground 0v
psb 4600 package outlines semiconductor group 8-1 preliminary data sheet 12.98 8 package outlines
psb 4600 precaution semiconductor group 9-1 preliminary data sheet 12.98 9 precaution ________________________________________ ________________________________________ overview: overview page absolute maximum ratings 9-2 dc characteristics 9-3 ac characteristics 9-5 capacitances 9-6
psb 4600 precaution semiconductor group 9-2 preliminary data sheet 12.98 9.1 absolute maximum ratings ________________________________________ ________________________________________ note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. this is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. ________________________________________ this table shows the parameters for the absolute maximum ratings parameter limit values unit voltage on any pin with respect to ground v s C 0.3 to v dd5 + 0.3 v ambient temperature under bias t a 0 to 70 c storage temperature t st g C 65 to 150 c maximum voltage on v dd3 /v dd5 v d d 7v
psb 4600 precaution semiconductor group 9-3 preliminary data sheet 12.98 9.2 dc characteristics ________________________________________ description the following dc characteristics are valid for all pins of the pita except the pci interface. ________________________________________ conditions t a = 0 to 70 c; v dd5 = 5 v 10 %, v dd3 = 3.3 v 10 %, v ss = 0 v; ________________________________________ dc characteristics parameter sym limit values unit test condition rem. min typ max l-input voltage v il C0.3 0.8 v h-input voltage v ih 2.0 v dd5 +0.3 v l-output voltage v ol 0.45 v i ol = 7 ma (txd, rxd) i ol = 2 ma (all others) h-output voltage v oh 2.4 v i oh = C 400 a v dd3 power supply current i cc 19 ma all power states except d3 cold (power off state) v dd5 power supply current i cc 1 ma all power states except d3 cold (power off state)
psb 4600 precaution semiconductor group 9-4 preliminary data sheet 12.98 ________________________________________ input leakage current i li 1 ua 0 v < v in < v dd5 1) output leakage current i lo 1 ua 0 v < v out < v dd5 1) (except for test , int0 which are internally pulled up (i li = 300 ua) and int1, clkrun which are internally pulled down (i lih = 500 ua) dc characteristics (contd) parameter sym limit values unit test condition rem. min typ max
psb 4600 precaution semiconductor group 9-5 preliminary data sheet 12.98 9.3 ac characteristics ________________________________________ description inputs are driven to 2,4 v for a logical 1 and to 0.45 v for a logical 0. timing measurements are made at 2.0 v for a logical 1 and 0.8 v for a logical 0. ________________________________________ conditions t a = 0 to 70 c, v dd5 = 5 v 10%, v dd3 = 3.3 v 10%, v ss = 0 v. ________________________________________ ac testing input/output waveform ________________________________________ device under test 2.4 0.45 2.0 0.8 2.0 0.8 test points c load =100pf
psb 4600 precaution semiconductor group 9-6 preliminary data sheet 12.98 9.4 capacitances ________________________________________ conditions t a = 25 c, v dd5 = 5 v 10%, v dd3 = 3.3 v 10%, v ss = 0 v, unmeasured pins grounded. ________________________________________ ________________________________________ capacitances parameter symbol limit values unit rem. min. max. input capacitance c in 7pf i/o capacitance c i/o 7pf
psb 4600 configuration space register of the pita semiconductor group 10-1 preliminary data sheet 12.98 10 configuration space register of the pita ________________________________________ ________________________________________ overview page description of the register types 10-2 configuration space register 10-3 registers which do not occur elsewhere in the data sheet 10-13
psb 4600 configuration space register of the pita semiconductor group 10-2 preliminary data sheet 12.98 10.1 description of the register types ________________________________________ ________________________________________ type description r read only ? these bits are initialized by pinstrapping during pci reset h read only ? hardwired rc read clear ? these bits are set by the internal logic ? these bits can be read out and reset by writing logical 1 to them ? writing logical 0 doesnt influence the states of these bits rw read write ? these bits can be read out and written via the pci bus ew eeprom write ? these bits can be set by an external eeprom after a system reset
psb 4600 configuration space register of the pita semiconductor group 10-3 preliminary data sheet 12.98 10.2 configuration space register ________________________________________ ________________________________________ 00h ad. bit type default value register name page 00h 31:16 h/ew 2104h device id 10-13 15:0 h/ew 110ah vendor id of siemens ag. 10-13 04h ad. bit type default value register name page 04h 31:0 0290 0000h pci status register 10-13 31 rc 0b parity error detected 10-13 30 rc 0b system error signaled 5-58 29 rc 0b master abort detected 5-58 28 rc 0b target abort detected 5-58 27 rc 0b target abort signaled 5-58 26:25 h 01b devsel timing 4-19 4-21 24 rc 0b data parity error reported 10-13 23 h 1b fast back-to-back capability 4-23 22 h 0b user defined functions 10-13 21 h 0b 66 mhz capability 10-13
psb 4600 configuration space register of the pita semiconductor group 10-4 preliminary data sheet 12.98 ________________________________________ ________________________________________ 20 h/ew 1b capabilities 10-13 19:16 h 0000b reserved 10-13 15:0 command register 10-13 15:10 h 000000b reserved 10-13 9 h 0b fast back-to-back enable 4-23 8 rw 0b system error enable 5-58 7 h 0b address/data stepping enable (not used) 10-13 6 rw 0b parity error response 10-13 5:3 h 000b the pita does not support the special cycle command. 10-13 2 rw 0b master enable 5-58 1 rw 0b memory access enable 4-8 0 h 0b i/o access enable 10-13 04h (contd) ad. bit type default value register name page 08h ad. bit type default value register name page 08h 31:8 h/ew 028000h class code/pci network device 10-16 7:0 h 01h revision id 10-16
psb 4600 configuration space register of the pita semiconductor group 10-5 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ ________________________________________ 0ch ad. bit type default value register name page 0ch 31:24 h 00h bist 10-17 23:16 h 00h header type 10-17 15:8 h 00h master latency timer 10-17 7:0 h 00h cache line size 10-17 10h ad. bit type default value register name page 10h 31:0 31:12 11:0 rw h 00000000h base register 0 4-8 14h ad. bit type default value register name page 14h 31:0 31:12 11:0 rw h 00000000h base register 1 4-9
psb 4600 configuration space register of the pita semiconductor group 10-6 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ ________________________________________ ________________________________________ 18h ad. bit type default value register name page 18h 31:0 h 00000000h base address register 2 (not used) 4-9 1ch ad. bit type default value register name page 1ch 31:0 h 00000000h base address register 3 (not used) 4-9 20h ad. bit type default value register name page 20h 31:0 h 00000000h base address register 4 (not used) 4-10 24h ad. bit type default value register name page 24h 31:0 h 00000000h base address register 5 (not used) 4-10
psb 4600 configuration space register of the pita semiconductor group 10-7 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ 28h ad. bit type default value register name page 28h 31:0 0000 02c0 cardbus cis pointer 4-11 31:28 h 0000b rom image number 4-11 27:3 h 000058h address space offset 4-11 2:0 h 000b address space indicator 4-12 2ch ad. bit type default value register name page 2ch 31:20 19:16 h/ew r or ew 000h pinstrap value or eeprom- value subsystem device id 4-12 15:0 r/ew pinstrap value or eeprom- value subsystem vendor id 4-12
psb 4600 configuration space register of the pita semiconductor group 10-8 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ ________________________________________ 30h ad. bit type default value register name page 30h 31:0 h 00000000h reserved 10-18 34h ad. bit type default value register name page 34h 31:8 h 00h reserved 4-28 7:0 h 40h capabilities pointer 4-28 38h ad. bit type default value register name page 38h 31:0 h 00000000h reserved 10-18 3ch ad. bit type default value register name page 3ch 31:24 h 00h max_lat 10-19 23:16 h 00h min_gnt 10-19
psb 4600 configuration space register of the pita semiconductor group 10-9 preliminary data sheet 12.98 ________________________________________ 15:8 h 01h interrupt pin 10-19 7:0 rw ffh interrupt line 10-19 3ch (contd) ad. bit type default value register name page 40h ad. bit type default value register name page 40h 31:0 1229 0001 power management capabilities (pmc) 4-28 31:30 29:28 27 h h/ew h 00b 01b 0b pme_support 4-28 26 h/ew 0b d2_support 4-28 25 h/ew 1b d1_support 4-28 24:22 h 000b reserved 4-28 21 h 1b dsi 4-28 20 h 0b reserved 4-28 19 h/ew 1b pme clock 4-28 18:16 h 001b version the value 001b indicates that the device complies with the revision 1.0 of the pci power management interface specification. 4-28 15:8 h 00h next item ptr 4-28
psb 4600 configuration space register of the pita semiconductor group 10-10 preliminary data sheet 12.98 ________________________________________ ________________________________________ 7:0 h 01h capability id 4-28 40h (contd) ad. bit type default value register name page 44h ad. bit type default value register name page 44h 31:24 h 00h data register 4-32 23:16 h 00h pmcsr_bse bridge support extensions 4-32 15:8 h 00h power management control/status register 4-32 15 rc 0b pme status 4-32 14:13 h 00b data scale 4-32 12:9 rw 0h data select 4-32 8 rw 0b pme_en 4-32 7:2 h 00h reserved 4-32 1:0 rw 00b power state 4-32 48h ad. bit type default value register name1 page 48h 31:0 power data register 1 10-20
psb 4600 configuration space register of the pita semiconductor group 10-11 preliminary data sheet 12.98 ________________________________________ 31:30 h 00b reserved 10-20 29:28 h/ew 00b data_scale in data_select = 2 10-20 27:20 h/ew 00h data in data_select = 2 10-20 19:18 h/ew 00b data_scale in data_select = 1 10-20 17:10 h/ew 00h data in data_select = 1 10-20 9:8 h/ew 00b data_scale in data_select = 0 10-20 7:0 h/ew 00h data in data_select = 0 10-20 48h (contd) ad. bit type default value register name1 page 4ch ad. bit type default value register name page 4ch 31:0 power data register 2 10-22 31:30 h 00b reserved 10-22 29:28 h/ew 00b data_scale in data_select = 5 10-22 27:20 h/ew 00h data in data_select = 5 10-22 19:18 h/ew 00b data_scale in data_select = 4 10-22 17:10 h/ew 00h data in data_select = 4 10-22 9:8 h/ew 00b data_scale in data_select = 3 10-22
psb 4600 configuration space register of the pita semiconductor group 10-12 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ 7:0 h/ew 00h data in data_select = 3 10-22 4ch (contd) ad. bit type default value register name page 50h ad. bit type default value register name page 50h 31:0 power data register 3 10-24 31:20 h 000h reserved 10-24 19:18 h/ew 00b data_scale in data_select = 7 10-24 17:10 h/ew 00h data_value in data_select = 7 10-24 9:8 h/ew 00b data_scale in data_select = 6 10-24 7:0 h/ew 00h data_value in data_select = 6 10-24 54h ad. bit type default value register name page 54h 31:0 h 00h cardbus cis 10-25
psb 4600 configuration space register of the pita semiconductor group 10-13 preliminary data sheet 12.98 10.3 registers which do not occur elsewhere in the data sheet ________________________________________ ________________________________________ 00h bit 31:16 device id type h or ew default value 2104h description identifies the pita within all pci devices from siemens semiconductors. bit 15:0 vendor id type h or ew default value 110ah description 110a is the vendor id of siemens ag. 04h bit 31:0 pci status register default value 02900000h bit 31 parity_error_detected type rc default value 0b description this bit is set, if a parity error is detected during a transaction with the pita. this is done independently from the status of the parity error response bit.
psb 4600 configuration space register of the pita semiconductor group 10-14 preliminary data sheet 12.98 bit 24 data_parity_error_reported type rc default value 0b description the pci master asserts this bit if it detects the perr signal on the pci bus asserted during a pci transaction initiated by itself. bit 22 user_defined_functions type h default value 0b description the pita has no user defined functions. bit 21 66_mhz_capability type h default value 0b description the pita is not a 66 mhz device (0 - 33 mhz supported.) bit 20 capabilities type h or ew default value 1b description if this bit is set, the pci device has additional capabilities defined in the pci configuration space header. additional capabilities can be found in the cap_ptr under address 34h. 04h (contd)
psb 4600 configuration space register of the pita semiconductor group 10-15 preliminary data sheet 12.98 bit 19:16 reserved type h default value 0000b description bit 15:0 command register bit 15:10 reserved type h default value 000000b description bit 7 address/data_stepping_enable type h default value 0b description not used bit 6 parity_error_response type rw default value 0b description if this bit is set to 1, the pci interface reports data parity errors by asserting the perr signal. 04h (contd)
psb 4600 configuration space register of the pita semiconductor group 10-16 preliminary data sheet 12.98 ________________________________________ ________________________________________ bit 5:3 type rw default value 0b description the pita does not support the special cycle command. the pita does not generate memory write and invalidate transactions. the pita does not support vga palette snooping. bit 0 i/o_access_enable type h default value 0b description the pci interface does not support i/o commands. 04h (contd) 08h bit 31:8 class_code type h or ew default value 028 000h description pci network device bit 7:0 revision id type h default value 01h description revision of the pci device
psb 4600 configuration space register of the pita semiconductor group 10-17 preliminary data sheet 12.98 ________________________________________ ________________________________________ 0ch bit 31:24 bist type h default value 00h description the pita has no built-in self test. bit 23:16 header_type type h default value 00h description bit 15:8 master_latency_timer type h default value 00h description unused bit 7:0 cache_line_size type h default value 00h description the pita does not support the cache line size register because it supports only single data transactions.
psb 4600 configuration space register of the pita semiconductor group 10-18 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ 30h bit 31:0 reserved type h default value 0000 0000h description reserved 38h bit 31:0 reserved type h default value 0000 0000h description
psb 4600 configuration space register of the pita semiconductor group 10-19 preliminary data sheet 12.98 ________________________________________ ________________________________________ 3ch bit 31:24 max_lat type h default value 00h description set to 0 because only single data transactions are supported. bit 23:16 mint_gnt type h default value 00h description set to 0 because only single data transactions are supported. bit 15:8 interrupt_pin type h default value 01h description as a single function device, the pita uses the inta signal. bit 7:0 interrupt_line type rw default value ffh description these bits show the interrupt line which is used by this system. for a x86 system the value ff means unknown. these registers are written during the initialization of the operating system.
psb 4600 configuration space register of the pita semiconductor group 10-20 preliminary data sheet 12.98 ________________________________________ 48h bit 31:0 power data register 1 bit 31:30 reserved type h default value 00b description reserved bit 29:28 data_scale in data_select=2 type h or ew default value 00b description this register is mapped to the data_scale field if data_select_field is set to 2. bit 27:20 data in data_select=2 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 2
psb 4600 configuration space register of the pita semiconductor group 10-21 preliminary data sheet 12.98 ________________________________________ bit 19:18 data_scale in data_select=1 type h or ew default value 00b description this register is mapped to the data_scale field if data_select field is set to1. bit 17:10 data in data_select=1 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 1. bit 9:8 data_scale in data_select=0 type h or ew default value 00b description this register is mapped to the data_scale field if data_select field is set to 0. bit 7:0 data in data_select=0 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 0. 48h (contd)
psb 4600 configuration space register of the pita semiconductor group 10-22 preliminary data sheet 12.98 ________________________________________ 4ch bit 31:0 power data register 2 bit 31:30 reserved type h default value 00b description reserved bit 29:28 data_scale in data_select=5 type h or ew default value 00b description this register is mapped to the data_scale field if data_select_field is set to 5. bit 27:20 data in data_select=5 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 5.
psb 4600 configuration space register of the pita semiconductor group 10-23 preliminary data sheet 12.98 ________________________________________ bit 19:18 data_scale in data_select=4 type h or ew default value 00b description this register is mapped to the data_scale field if data_select field is set to 4 bit 17:10 data in data_select=4 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 4. bit 9:8 data_scale in data_select=3 type h or ew default value 00b description this register is mapped to the data_scale field if data_select field is set to 3- bit 7:0 data in data_select=3 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 3. 4ch (contd)
psb 4600 configuration space register of the pita semiconductor group 10-24 preliminary data sheet 12.98 ________________________________________ 50h bit 31:0 power data register 3 bit 31:30 reserved type h default value 00b description reserved bit 19:18 data_scale in data_select=7 type h or ew default value 00b description this register is mapped to the data_scale field if data_select field is set to 7. bit 17:10 data in data_select=7 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 7.
psb 4600 configuration space register of the pita semiconductor group 10-25 preliminary data sheet 12.98 ________________________________________ ________________________________________ bit 9:8 data_scale in data_select=6 type h or ew default value 00b description this register is mapped to the data_scale field if data_select field is set to 6. bit 7:0 data in data_select=6 type h or ew default value 00h description this register is mapped to the data register if the data_select field is set to 6. 50h (contd) 54h bit 31:0 cardbus_cis type h default value 00h description default value: 00h up from this register, the cardbus cis structure is implemented (not supported in this version of pita)
psb 4600 internal register of the pita semiconductor group 11-1 preliminary data sheet 12.98 11 internal register of the pita ________________________________________ ________________________________________ overview page description of the register types 11-2 internal register 11-3 registers which do not occur elsewhere in the data sheet 11-10
psb 4600 internal register of the pita semiconductor group 11-2 preliminary data sheet 12.98 11.1 description of the register types ________________________________________ ________________________________________ type description r read only ? these bits are initialized by pinstrapping during pci reset h read only ? hardwired rc read clear ? these bits are set by the internal logic ? these bits can be read out and reset by writing logical 1 to them ? writing logical 0 doesnt influence the states of these bits rw read write ? these bits can be read out and written via the pci bus ew eeprom write ? these bits can be set by an external eeprom after a system reset
psb 4600 internal register of the pita semiconductor group 11-3 preliminary data sheet 12.98 11.2 internal register ________________________________________ 00h ad. bit type default value register name page 00h 31:0 00000000h icr - interrupt control register 11-10 31:29 h 000b reserved 11-10 28 rw 0b eeprom_control_int_en 5-90 27 rw 0b retry_counter_down_ int_en 4-35 26 rw 0b fifo_overflow_empty_ int_en 5-10 25 rw 0b dma_write_counter_ overflow_int_en 5-10 24 rw 0b dma_write_counter_int_ en 5-10 23:18 h 000000b reserved 11-10 17 rw 0b int0_en 11-10 16 rw 0b int1_ en 11-10 15:13 h 000b reserved 11-10 12 rc 0b eeprom_control_int 5-90 11 rc 0b retry_counter_int 4-35 10 rc 0b fifo_overflow_empty_ int 5-10 9 rc 0b dma_write_counter_ overflow_int 5-10 8 rc 0b dma_write_counter_int 5-10
psb 4600 internal register of the pita semiconductor group 11-4 preliminary data sheet 12.98 ________________________________________ 7:6 h 0b reserved 11-10 5rc0b gp3_int 5-69 4rc0b gp2_int 5-69 3rc0b gp1_int 5-69 2rc0b gp0_int 5-69 1rc0b int0 11-10 0rc0b int1 11-10 00h (contd) ad. bit type default value register name page 04h ad. bit type default value register name page 04h 31:0 00000000h dma control register 5-11 31:09 h 0000000h reserved 5-11 8 rw 0b dma start 5-11 7:6 h 00b reserved 5-11 5:0 rw 000000b dma select - all modes iom-2 mode 1 iom-2 mode 2 iom-2 mode 3 single modem mode v2.1 single modem mode v3.x dual modem+voice mode 5-11 5-16 5-20 5-23 5-31 5-36 5-44
psb 4600 internal register of the pita semiconductor group 11-5 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ ________________________________________ 08h ad. bit type default value register name page 08h 31:12 11:0 rw h 00000h 000h circular buffer start address 5-13 0ch ad. bit type default value register name page 0ch 31:02 1:0 r h 00000000h 00b actual circular buffer pointer 5-13 10h ad. bit type default value register name page 10h 31:0 00000000h alis command register 1 5-36 31:25 h 00h reserved 5-36 24 rw 0b new_alis_command_1 5-36 23:16 rw 00h alis_received_data_1 5-36 15:8 rw 00h alis_command_1 5-36 7:0 rw 0b alis_transmit_data_1 5-36
psb 4600 internal register of the pita semiconductor group 11-6 preliminary data sheet 12.98 ________________________________________ ________________________________________ 14h ad. bit type default value register name page 14h 31:0 00000000h alis command register 2 5-39 32:25 h 000h reserved 5-39 24 rw 0b new_alis_command_2 5-39 23:16 rw 00h alis_received_data_2 5-39 15:8 rw 00h alis_command_2 5-39 7:0 rw 00h alis_transmit_data_2 5-39 18h ad. bit type default value register name page 18h 31:0 00000000h gp i/o interface control register 5-70 31:28 h 0h reserved 5-70 27 rw 0b gp3_int_en 5-70 26 rw 0b gp2_int_en 5-70 25 rw 0b gp1_int_en 5-70 24 rw 0b gp0_int_en 5-70 23:20 h 0000b reserved 5-70 19 rw 0b gp3_out_en 5-70 18 rw 0b gp2_out_en 5-70
psb 4600 internal register of the pita semiconductor group 11-7 preliminary data sheet 12.98 ________________________________________ 17 rw 0b gp1_out_en 5-70 16 rw 0b gp0_out_en 5-70 15:12 h 0000b reserved 5-70 11 r 0b gp3_in 5-70 10 r 0b gp2_in 5-70 9 r 0b gp1_in 5-70 8 r 0b gp0_in 5-70 7:4 h 0000b reserved 5-70 3 rw 0b gp3_out 5-70 2 rw 0b gp2_out 5-70 1 rw 0b gp1_out 5-70 0 rw 0b gp0_out 5-70 18h (contd) ad. bit type default value register name page 1ch ad. bit type default value register name page 1ch 31:0 00000000h misc - miscellaneous register 5-27 31 rw 0b iom b1 masking 5-27 30 rw 0b iom b2 masking 5-27 29 rw 0b iom mon0/ic1 masking 5-27 28 rw 0b iom d+c/i0+mr+mx / ic2 masking 5-27
psb 4600 internal register of the pita semiconductor group 11-8 preliminary data sheet 12.98 ________________________________________ 27 rw 1b serial interface buffer mode 11-12 26 rw 0b parallel interface mode 5-47 25 rw 0b soft reset serial interface 11-12 24 rw 0b soft reset parallel interface 5-47 23:16 rw 00h retry count register 4-36 15:12 h 0000b reserved 11-12 11:0 rw 0000h dma write count register 5-14 1ch (contd) ad. bit type default value register name page 20h ad. bit type default value register name page 20h 31:0 00000000h serial clock select register 31:2 h 00000000h reserved 1 rw 0b dcl_out_en 5-17 5-20 5-23 5-32 5-41 0 rw 0b serial_clock_sel 5-17 5-20 5-23 5-32 5-41
psb 4600 internal register of the pita semiconductor group 11-9 preliminary data sheet 12.98 ________________________________________ ________________________________________ ________________________________________ 24h ad. bit type default value register name page 24h 31:0 00000000h eeprom control register 5-90 31:25 h 0000h reserved 5-90 24 rw 0b eeprom start 5-90 23:16 rw 00h eeprom command 5-90 15:8 rw 00h eeprom byte address 5-90 7:0 rw 00h eeprom data 5-90 28h ad. bit type default value register name page 28h 31:0 00000000h dma test register 11-12 31:01 h 00000000h reserved 11-12 0 rw 0b loop_back_mode 5-46
psb 4600 internal register of the pita semiconductor group 11-10 preliminary data sheet 12.98 11.3 registers which do not occur elsewhere in the data sheet ________________________________________ 00h bit 31:0 icr - interrupt control register default value 00000000h description the interrupt enable bits for gp3-0 are placed in the gp i/o interface control register. all interrupt enables are high active: int_en=0 -> corresponding interrupt (bit) is disabled int_en=1 -> corresponding interrupt (bit) is enables bit 31:29 reserved type h default value 000b description reserved bit 23:18 reserved type h default value 000000b description reserved bit 17 int0_en type rw default value 0b description enable for the int0 interrupt bit.
psb 4600 internal register of the pita semiconductor group 11-11 preliminary data sheet 12.98 ________________________________________ bit 16 int_en type rw default value 0b description enable for the int1 interrupt bit. bit 23:18 reserved type h default value 000000b description reserved bit 1 int0 type rc default value 0b description an interrupt is detected on pin int0 (low active). bit 0 int1 type rc default value 0b description an interrupt is detected on pin int1 (low active). 00h (contd)
psb 4600 internal register of the pita semiconductor group 11-12 preliminary data sheet 12.98 ________________________________________ ________________________________________ 1ch bit 27 serial interface buffer mode type rw default value 1b description bit 27=0: the txd pin is configured as push/pull output pin. bit 27=1: the txd pin is configured as open drain output pin. bit 25 soft reset serial interface type rw default value 0b description bit 25=0: activates the low active reset signal srst to the application. bit 25=1: deactivates the reset signal srst to the application. before asserting this bit the dma_start bit has to be reset. 28h bit 31:0 dma test register default value 00000000h bit 31:1 reserved type h default value 00000000h description reserved
psb 4600 abbreviations semiconductor group 13 preliminary data sheet 12.98 12 abbreviations ac alternating current. a/d analog to digital. adc analog to digital converter. ale address latch enable. alis analog line interface solution. chip set consisting of psb4595 and psb4596. dc direct current. dcl double bit clock. (in this context, only in the iom-2 modes of the serial interface of the pita, single bit in all other modes). dma direct memory access. dd data downstream. du data upstream. eeprom = e 2 prom electrically erasable programmable read only memory. fifo rx fifo tx fifo first in first out. fsc frame sync. i/o in/out. iom isdn oriented modular. isdn integrated services digital network. msb most significant bit. pita pci interface for telephony/data applications. pci peripheral component interconnect. rxd receive direction. txd transmit direction.
psb 4600 index semiconductor group 13-1 preliminary data sheet 12.98 13 index numerics 3pac 2-2 a absolute maximum ratings 9-2 ac characteristics 9-5 ale after internal softreset 5-51 ale after setting the parallel interface mode bit 5-52 ale after system reset 5-50 alis v2.1 1-2 connection to the serial control interface 5-87 pita configuration after a system reset 5-31 alis v3.x 1-2 pita configuration after a system reset 5-35 alis-a 2-2 alis-d 2-2 b base address register 4-7 structure of the address space 4-7 c capacitances 9-6 configuration space register 10-3 00h 10-3 04h 10-3 08h 10-4 0ch 10-5 10h 10-5 14h 10-5 18h 10-6 1ch 10-6 20h 10-6 24h 10-6 28h 10-7 2ch 10-7 30h 10-8 34h 10-8 38h 10-8 3ch 10-8 40h 10-9 44h 10-10 48h 10-10 50h 10-12 54h 10-12 base address register 0 10h 4-8 base address register 1 14h 4-9 base address register 2 18h 4-9 base address register 3 1ch 4-9 base address register 4 20h 4-10 base address register 5 28h 4-10 base address registert 04h 4-8 burst read 04h 4-19 burst write 04h 4-21 disconnect with target abort 04h 5-58 do not occur in the data sheet 00h 10-13 04h 10-13 08h 10-16 0ch 10-17 30h 10-18 38h 10-8, 10-18 3ch 10-19 48h 10-20 4ch 10-22 50h 10-24
psb 4600 index semiconductor group 13-2 preliminary data sheet 12.98 54h 10-25 fast back to back 04h 4-23 pci configuration space special qualities 28h 4-11 2ch 4-12 power management 34h 4-28 40h 4-28 44h 4-32 d dc characteristics 9-3 dma algorithm function 5-6 dma controller 5-4 function 5-5 dma start bit 5-7 dma write counter 5-6 dual modem/modem+voice mode 5-42 e electrical characteristics power management states 4-27 g general purpose i/o interface 5-65 input mode 5-76 interrupt mode 5-80 output mode 5-78 pinning 7-7 i iec-q te 1-2, 2-2 interfaces general purpose i/o interface 5-65 parallel interface 5-47 serial dma interface 5-2 spi eeprom interface 5-84 internal register 00h 10-5, 11-3 04h 11-4 08h 11-5 0ch 11-5 10h 11-5 14h 11-6 18h 11-6 1ch 11-7 20h 11-8 24h 11-9 28h 11-9 4ch 10-11 alis 10h 5-36 14h 5-39 dma controller 00h 5-10 04h 5-11, 5-13, 5-31, 5-36, 5- 38, 5-44 08h 5-13 0ch 5-13, 5-14, 5-46, 5-47, 5-70 1ch 5-14 do not occur in the data sheet 00h 11-10 1ch 11-12 28h 11-12 gp i/o interface 00h 5-69 18h 5-70 iom-2 mode 1 04h 5-16, 5-20, 5-23 iom-2 modes 1ch 5-27 loopback mode 28h 5-46 parallel interface 1ch 5-47 retry counter 00h 4-35 1ch 4-36 single modem mode v2.1 20h 5-41 single modem mode v2.1 20h 5-17, 5-20, 5-23, 5-32 spi eeprom interface
psb 4600 index semiconductor group 13-3 preliminary data sheet 12.98 00h 5-36, 5-39, 5-90 24h 5-90 interrupt control register 4-35 interrupts fifo overflow/empty 5-9 write counter 5-9 iom-2 mode 1 5-15 iom-2 mode 2 5-18 iom-2 mode 3 5-21 iom-2 modes general description 5-24 masking of iom-2 timeslots 5-26 selection of iom-2 timeslots 5-24 ipac 1-2, 2-1 isac 1-2 isar 1-2, 2-3 isdn modem using isar 2-3 -s with ipac 2-1 -u with 3pac and iec-q te 2-2 l loopback mode 5-45 m multiplexed mode read transaction 5-56 multiplexed mode write transaction 5-55 n non multiplexed mode read transaction 5-54 write transaction 5-53 p parallel interface 5-47 pinning 7-4 pc98 1-1 pci bus pinning 7-3 pci commands 4-14 pci configuration space 4-2 access to the 4-6 construction of 4-4 pci master controller supported pci commands 4-14 pci master target controller 4-13 pci target controller supported pci commands 4-14 pinning description of pin types 7-2 gp i/o interface 7-7 parallel interfaces 7-4 power supply 7-9 serial interface 7-6 special eeprom signals 7-8 test if 7-8 pinstrapping 6-1 power management 4-24 power management state d0 4-25 d1 4-25 d2 4-25 d3 4-26 d3cold 4-26 d3hot 4-26 power management states electrical characteristics 4-27 power supply pinning 7-9 s serial dma interface 5-2 serial interface pinning 7-6 single modem mode v2.1 5-29 configuration after a system/soft reset 5-30 single modem mode v3.x 5-33 configuration after a system/soft reset 5-35 software modem using alis-a and alis-d 2-2 special eeprom signals pinning 7-8 spi eeprom interface 5-84
psb 4600 index semiconductor group 13-4 preliminary data sheet 12.98 after finishing the transaction 5-87 starting a read or write transaction 5- 86 t test if pinning 7-8 timing 5-57 timing diagram ale after internal softreset 5-51 ale after setting the parallel interface mode bit 5-52 ale after system reset 5-50 burst read 4-18 burst write 4-20 dual modem/modem+voice mode 5-43 fast back to back 4-22 gp i/o interface alis v2.1 read 5-83 alis v2.1 write 5-83 input mode 5-76 interrupt mode 5-80 output mode 5-79 iom-2 all modes 5-24 iom-2 mode 1 5-16 iom-2 mode 2 5-19 iom-2 mode 3 5-22 loopback mode 5-45 multiplexed mode read 5-56 multiplexed mode write 5-55 non multiplexed mode read 5-54 non multiplexed mode write 5-53 parallel interface multiplexed address 5-62 non mulitplexed address 5-63 read 5-62 write 5-62 single data read 4-16 single data write 4-17 single modem mode v2.1 5-29 single modem mode v3.x 5-34 spi eeprom interface 5-88 transaction disconnect 5-57 transaction termination 5-60 transaction disconnect 5-57 transaction termination with retry 5-60

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